mirror of https://github.com/acidanthera/audk.git
583 lines
22 KiB
C
583 lines
22 KiB
C
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/** @file
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Unit Test Host BaseLib hooks.
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Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __UNIT_TEST_HOST_BASE_LIB_H__
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#define __UNIT_TEST_HOST_BASE_LIB_H__
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/**
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Prototype of service with no parameters and no return value.
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**/
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typedef
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VOID
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_VOID)(
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VOID
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);
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/**
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Prototype of service that reads and returns a BOOLEAN value.
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@return The value read.
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**/
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typedef
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BOOLEAN
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN)(
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VOID
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);
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/**
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Prototype of service that reads and returns a UINT16 value.
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@return The value read.
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**/
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typedef
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UINT16
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINT16)(
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VOID
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);
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/**
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Prototype of service that reads and returns a UINTN value.
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@return The value read.
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**/
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typedef
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UINTN
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINTN)(
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VOID
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);
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/**
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Prototype of service that writes and returns a UINT16 value.
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@param[in] Value The value to write.
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@return The value written.
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**/
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typedef
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VOID
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16)(
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IN UINT16 Value
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);
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/**
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Prototype of service that writes and returns a UINTN value.
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@param[in] Value The value to write.
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@return The value written.
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**/
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typedef
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UINTN
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN)(
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IN UINTN Value
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);
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/**
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Prototype of service that reads and returns an IA32_DESCRIPTOR.
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@param[out] Ia32Descriptor Pointer to the descriptor read.
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**/
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typedef
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VOID
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR)(
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OUT IA32_DESCRIPTOR *Ia32Descriptor
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);
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/**
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Prototype of service that writes an IA32_DESCRIPTOR.
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@param[in] Ia32Descriptor Pointer to the descriptor to write.
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**/
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typedef
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VOID
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR)(
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IN CONST IA32_DESCRIPTOR *Ia32Descriptor
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);
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/**
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Retrieves CPUID information.
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Executes the CPUID instruction with EAX set to the value specified by Index.
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This function always returns Index.
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If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
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If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
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If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
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If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
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This function is only available on IA-32 and x64.
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@param Index The 32-bit value to load into EAX prior to invoking the CPUID
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instruction.
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@param Eax The pointer to the 32-bit EAX value returned by the CPUID
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instruction. This is an optional parameter that may be NULL.
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@param Ebx The pointer to the 32-bit EBX value returned by the CPUID
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instruction. This is an optional parameter that may be NULL.
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@param Ecx The pointer to the 32-bit ECX value returned by the CPUID
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instruction. This is an optional parameter that may be NULL.
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@param Edx The pointer to the 32-bit EDX value returned by the CPUID
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instruction. This is an optional parameter that may be NULL.
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@return Index.
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**/
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typedef
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UINT32
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID)(
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IN UINT32 Index,
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OUT UINT32 *Eax, OPTIONAL
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OUT UINT32 *Ebx, OPTIONAL
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OUT UINT32 *Ecx, OPTIONAL
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OUT UINT32 *Edx OPTIONAL
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);
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/**
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Retrieves CPUID information using an extended leaf identifier.
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Executes the CPUID instruction with EAX set to the value specified by Index
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and ECX set to the value specified by SubIndex. This function always returns
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Index. This function is only available on IA-32 and x64.
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If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
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If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
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If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
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If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
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@param Index The 32-bit value to load into EAX prior to invoking the
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CPUID instruction.
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@param SubIndex The 32-bit value to load into ECX prior to invoking the
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CPUID instruction.
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@param Eax The pointer to the 32-bit EAX value returned by the CPUID
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instruction. This is an optional parameter that may be
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NULL.
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@param Ebx The pointer to the 32-bit EBX value returned by the CPUID
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instruction. This is an optional parameter that may be
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NULL.
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@param Ecx The pointer to the 32-bit ECX value returned by the CPUID
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instruction. This is an optional parameter that may be
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NULL.
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@param Edx The pointer to the 32-bit EDX value returned by the CPUID
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instruction. This is an optional parameter that may be
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NULL.
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@return Index.
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**/
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typedef
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UINT32
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX)(
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IN UINT32 Index,
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IN UINT32 SubIndex,
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OUT UINT32 *Eax, OPTIONAL
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OUT UINT32 *Ebx, OPTIONAL
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OUT UINT32 *Ecx, OPTIONAL
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OUT UINT32 *Edx OPTIONAL
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);
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/**
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Returns a 64-bit Machine Specific Register(MSR).
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Reads and returns the 64-bit MSR specified by Index. No parameter checking is
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performed on Index, and some Index values may cause CPU exceptions. The
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caller must either guarantee that Index is valid, or the caller must set up
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exception handlers to catch the exceptions. This function is only available
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on IA-32 and x64.
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@param Index The 32-bit MSR index to read.
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@return The value of the MSR identified by Index.
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**/
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typedef
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UINT64
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64)(
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IN UINT32 Index
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);
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/**
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Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
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value.
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Writes the 64-bit value specified by Value to the MSR specified by Index. The
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64-bit value written to the MSR is returned. No parameter checking is
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performed on Index or Value, and some of these may cause CPU exceptions. The
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caller must either guarantee that Index and Value are valid, or the caller
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must establish proper exception handlers. This function is only available on
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IA-32 and x64.
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@param Index The 32-bit MSR index to write.
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@param Value The 64-bit value to write to the MSR.
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@return Value
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**/
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typedef
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UINT64
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64)(
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IN UINT32 Index,
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IN UINT64 Value
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);
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/**
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Reads the current value of a Performance Counter (PMC).
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Reads and returns the current value of performance counter specified by
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Index. This function is only available on IA-32 and x64.
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@param Index The 32-bit Performance Counter index to read.
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@return The value of the PMC specified by Index.
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**/
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typedef
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UINT64
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC)(
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IN UINT32 Index
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);
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/**
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Sets up a monitor buffer that is used by AsmMwait().
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Executes a MONITOR instruction with the register state specified by Eax, Ecx
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and Edx. Returns Eax. This function is only available on IA-32 and x64.
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@param Eax The value to load into EAX or RAX before executing the MONITOR
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instruction.
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@param Ecx The value to load into ECX or RCX before executing the MONITOR
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instruction.
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@param Edx The value to load into EDX or RDX before executing the MONITOR
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instruction.
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@return Eax
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**/
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typedef
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UINTN
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR)(
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IN UINTN Eax,
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IN UINTN Ecx,
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IN UINTN Edx
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);
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/**
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Executes an MWAIT instruction.
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Executes an MWAIT instruction with the register state specified by Eax and
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Ecx. Returns Eax. This function is only available on IA-32 and x64.
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@param Eax The value to load into EAX or RAX before executing the MONITOR
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instruction.
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@param Ecx The value to load into ECX or RCX before executing the MONITOR
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instruction.
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@return Eax
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**/
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typedef
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UINTN
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT)(
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IN UINTN Eax,
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IN UINTN Ecx
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);
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/**
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Flushes a cache line from all the instruction and data caches within the
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coherency domain of the CPU.
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Flushed the cache line specified by LinearAddress, and returns LinearAddress.
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This function is only available on IA-32 and x64.
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@param LinearAddress The address of the cache line to flush. If the CPU is
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in a physical addressing mode, then LinearAddress is a
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physical address. If the CPU is in a virtual
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addressing mode, then LinearAddress is a virtual
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address.
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@return LinearAddress.
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**/
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typedef
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VOID *
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(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE)(
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IN VOID *LinearAddress
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);
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|
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/**
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Prototype of service that enables ot disables 32-bit paging modes.
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|
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@param EntryPoint A pointer to function to call with the new stack after
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paging is enabled.
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@param Context1 A pointer to the context to pass into the EntryPoint
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function as the first parameter after paging is enabled.
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@param Context2 A pointer to the context to pass into the EntryPoint
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function as the second parameter after paging is enabled.
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@param NewStack A pointer to the new stack to use for the EntryPoint
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|
function after paging is enabled.
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||
|
|
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**/
|
||
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|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32)(
|
||
|
|
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
|
||
|
|
IN VOID *Context1, OPTIONAL
|
||
|
|
IN VOID *Context2, OPTIONAL
|
||
|
|
IN VOID *NewStack
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||
|
|
);
|
||
|
|
|
||
|
|
/**
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||
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Enables the 64-bit paging mode on the CPU.
|
||
|
|
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||
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|
Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
|
||
|
|
must be properly initialized prior to calling this service. This function
|
||
|
|
assumes the current execution mode is 32-bit protected mode with flat
|
||
|
|
descriptors. This function is only available on IA-32. After the 64-bit
|
||
|
|
paging mode is enabled, control is transferred to the function specified by
|
||
|
|
EntryPoint using the new stack specified by NewStack and passing in the
|
||
|
|
parameters specified by Context1 and Context2. Context1 and Context2 are
|
||
|
|
optional and may be 0. The function EntryPoint must never return.
|
||
|
|
|
||
|
|
If the current execution mode is not 32-bit protected mode with flat
|
||
|
|
descriptors, then ASSERT().
|
||
|
|
If EntryPoint is 0, then ASSERT().
|
||
|
|
If NewStack is 0, then ASSERT().
|
||
|
|
|
||
|
|
@param Cs The 16-bit selector to load in the CS before EntryPoint
|
||
|
|
is called. The descriptor in the GDT that this selector
|
||
|
|
references must be setup for long mode.
|
||
|
|
@param EntryPoint The 64-bit virtual address of the function to call with
|
||
|
|
the new stack after paging is enabled.
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||
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|
@param Context1 The 64-bit virtual address of the context to pass into
|
||
|
|
the EntryPoint function as the first parameter after
|
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|
|
paging is enabled.
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||
|
|
@param Context2 The 64-bit virtual address of the context to pass into
|
||
|
|
the EntryPoint function as the second parameter after
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||
|
|
paging is enabled.
|
||
|
|
@param NewStack The 64-bit virtual address of the new stack to use for
|
||
|
|
the EntryPoint function after paging is enabled.
|
||
|
|
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||
|
|
**/
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||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64)(
|
||
|
|
IN UINT16 Cs,
|
||
|
|
IN UINT64 EntryPoint,
|
||
|
|
IN UINT64 Context1, OPTIONAL
|
||
|
|
IN UINT64 Context2, OPTIONAL
|
||
|
|
IN UINT64 NewStack
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||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Disables the 64-bit paging mode on the CPU.
|
||
|
|
|
||
|
|
Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
|
||
|
|
mode. This function assumes the current execution mode is 64-paging mode.
|
||
|
|
This function is only available on x64. After the 64-bit paging mode is
|
||
|
|
disabled, control is transferred to the function specified by EntryPoint
|
||
|
|
using the new stack specified by NewStack and passing in the parameters
|
||
|
|
specified by Context1 and Context2. Context1 and Context2 are optional and
|
||
|
|
may be 0. The function EntryPoint must never return.
|
||
|
|
|
||
|
|
If the current execution mode is not 64-bit paged mode, then ASSERT().
|
||
|
|
If EntryPoint is 0, then ASSERT().
|
||
|
|
If NewStack is 0, then ASSERT().
|
||
|
|
|
||
|
|
@param Cs The 16-bit selector to load in the CS before EntryPoint
|
||
|
|
is called. The descriptor in the GDT that this selector
|
||
|
|
references must be setup for 32-bit protected mode.
|
||
|
|
@param EntryPoint The 64-bit virtual address of the function to call with
|
||
|
|
the new stack after paging is disabled.
|
||
|
|
@param Context1 The 64-bit virtual address of the context to pass into
|
||
|
|
the EntryPoint function as the first parameter after
|
||
|
|
paging is disabled.
|
||
|
|
@param Context2 The 64-bit virtual address of the context to pass into
|
||
|
|
the EntryPoint function as the second parameter after
|
||
|
|
paging is disabled.
|
||
|
|
@param NewStack The 64-bit virtual address of the new stack to use for
|
||
|
|
the EntryPoint function after paging is disabled.
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64)(
|
||
|
|
IN UINT16 Cs,
|
||
|
|
IN UINT32 EntryPoint,
|
||
|
|
IN UINT32 Context1, OPTIONAL
|
||
|
|
IN UINT32 Context2, OPTIONAL
|
||
|
|
IN UINT32 NewStack
|
||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Retrieves the properties for 16-bit thunk functions.
|
||
|
|
|
||
|
|
Computes the size of the buffer and stack below 1MB required to use the
|
||
|
|
AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
|
||
|
|
buffer size is returned in RealModeBufferSize, and the stack size is returned
|
||
|
|
in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
|
||
|
|
then the actual minimum stack size is ExtraStackSize plus the maximum number
|
||
|
|
of bytes that need to be passed to the 16-bit real mode code.
|
||
|
|
|
||
|
|
If RealModeBufferSize is NULL, then ASSERT().
|
||
|
|
If ExtraStackSize is NULL, then ASSERT().
|
||
|
|
|
||
|
|
@param RealModeBufferSize A pointer to the size of the buffer below 1MB
|
||
|
|
required to use the 16-bit thunk functions.
|
||
|
|
@param ExtraStackSize A pointer to the extra size of stack below 1MB
|
||
|
|
that the 16-bit thunk functions require for
|
||
|
|
temporary storage in the transition to and from
|
||
|
|
16-bit real mode.
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES)(
|
||
|
|
OUT UINT32 *RealModeBufferSize,
|
||
|
|
OUT UINT32 *ExtraStackSize
|
||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Prototype of services that operates on a THUNK_CONTEXT structure.
|
||
|
|
|
||
|
|
@param ThunkContext A pointer to the context structure that describes the
|
||
|
|
16-bit real mode code to call.
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16)(
|
||
|
|
IN OUT THUNK_CONTEXT *ThunkContext
|
||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Patch the immediate operand of an IA32 or X64 instruction such that the byte,
|
||
|
|
word, dword or qword operand is encoded at the end of the instruction's
|
||
|
|
binary representation.
|
||
|
|
|
||
|
|
This function should be used to update object code that was compiled with
|
||
|
|
NASM from assembly source code. Example:
|
||
|
|
|
||
|
|
NASM source code:
|
||
|
|
|
||
|
|
mov eax, strict dword 0 ; the imm32 zero operand will be patched
|
||
|
|
ASM_PFX(gPatchCr3):
|
||
|
|
mov cr3, eax
|
||
|
|
|
||
|
|
C source code:
|
||
|
|
|
||
|
|
X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
|
||
|
|
PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
|
||
|
|
|
||
|
|
@param[out] InstructionEnd Pointer right past the instruction to patch. The
|
||
|
|
immediate operand to patch is expected to
|
||
|
|
comprise the trailing bytes of the instruction.
|
||
|
|
If InstructionEnd is closer to address 0 than
|
||
|
|
ValueSize permits, then ASSERT().
|
||
|
|
|
||
|
|
@param[in] PatchValue The constant to write to the immediate operand.
|
||
|
|
The caller is responsible for ensuring that
|
||
|
|
PatchValue can be represented in the byte, word,
|
||
|
|
dword or qword operand (as indicated through
|
||
|
|
ValueSize); otherwise ASSERT().
|
||
|
|
|
||
|
|
@param[in] ValueSize The size of the operand in bytes; must be 1, 2,
|
||
|
|
4, or 8. ASSERT() otherwise.
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86)(
|
||
|
|
OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
|
||
|
|
IN UINT64 PatchValue,
|
||
|
|
IN UINTN ValueSize
|
||
|
|
);
|
||
|
|
|
||
|
|
///
|
||
|
|
/// Common services
|
||
|
|
///
|
||
|
|
typedef struct {
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState;
|
||
|
|
} UNIT_TEST_HOST_BASE_LIB_COMMON;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// IA32/X64 services
|
||
|
|
///
|
||
|
|
typedef struct {
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Properties;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk16;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86;
|
||
|
|
} UNIT_TEST_HOST_BASE_LIB_X86;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// Data structure that contains pointers structures of common services and CPU
|
||
|
|
/// architctuire specific services. Support for additional CPU architectures
|
||
|
|
/// can be added to the end of this structure.
|
||
|
|
///
|
||
|
|
typedef struct {
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_COMMON *Common;
|
||
|
|
UNIT_TEST_HOST_BASE_LIB_X86 *X86;
|
||
|
|
} UNIT_TEST_HOST_BASE_LIB;
|
||
|
|
|
||
|
|
extern UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib;
|
||
|
|
|
||
|
|
#endif
|