mirror of https://github.com/acidanthera/audk.git
94 lines
2.4 KiB
OpenEdge ABL
94 lines
2.4 KiB
OpenEdge ABL
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// Copyright (c) 2006, Intel Corporation
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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// Module Name:
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//
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// IpfCpuCore.i
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//
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// Abstract:
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// IPF CPU definitions
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//
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//--
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#ifndef _IPF_CPU_CORE_
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#define _IPF_CPU_CORE_
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#define PEI_BSP_STORE_SIZE 0x4000
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#define ResetFn 0x00
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#define MachineCheckFn 0x01
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#define InitFn 0x02
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#define RecoveryFn 0x03
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#define GuardBand 0x10
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//
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// Define hardware RSE Configuration Register
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//
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//
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// RS Configuration (RSC) bit field positions
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//
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#define RSC_MODE 0
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#define RSC_PL 2
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#define RSC_BE 4
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//
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// RSC bits 5-15 reserved
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//
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#define RSC_MBZ0 5
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#define RSC_MBZ0_V 0x3ff
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#define RSC_LOADRS 16
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#define RSC_LOADRS_LEN 14
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//
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// RSC bits 30-63 reserved
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//
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#define RSC_MBZ1 30
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#define RSC_MBZ1_V 0x3ffffffffULL
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//
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// RSC modes
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//
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//
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// Lazy
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//
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#define RSC_MODE_LY (0x0)
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//
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// Store intensive
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//
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#define RSC_MODE_SI (0x1)
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//
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// Load intensive
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//
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#define RSC_MODE_LI (0x2)
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//
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// Eager
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//
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#define RSC_MODE_EA (0x3)
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//
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// RSC Endian bit values
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//
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#define RSC_BE_LITTLE 0
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#define RSC_BE_BIG 1
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//
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// RSC while in kernel: enabled, little endian, pl = 0, eager mode
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//
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#define RSC_KERNEL ((RSC_MODE_EA<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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//
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// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
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//
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#define RSC_KERNEL_LAZ ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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//
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// RSE disabled: disabled, pl = 0, little endian, eager mode
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//
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#define RSC_KERNEL_DISABLED ((RSC_MODE_LY<<RSC_MODE) | (RSC_BE_LITTLE<<RSC_BE))
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#endif
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