tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
audk/BaseTools/Scripts/Rvct-Align4K.sct

20 lines
276 B
Plaintext
Raw Normal View History

BaseTools RVCT: use scatter file to enforce minimum section alignment Up until SVN r18540, GenFw created invalid PE/COFF binaries for the ARM architecture, by allowing PE/COFF .data sections to appear at offsets that were not aligned to the global PE/COFF section alignment. The reason for this was that the relocation metadata emitted by RVCT's armlink only contains dynamic absolute relocations, so it is impossible to recalculate relative relocations between .text and .data, and so the relative offset between the two needs to be preserved. Since r18540, we do align .data to the PE/COFF section alignment, resulting in potentially corrupt PE/COFF binaries unless .data happens to appear at a 32-byte aligned offset. So let's introduce a RVCT scatter file that sets this alignment for the ELF .data section (and subsequent .bss section). At the same time, set the start offset to 0x220 bytes (which is the size of our 32-bit PE/COFF header) so that the memory layouts are identical between ELF and PE/COFF. Also add a 4 KB aligned version that can be used to build DXE_RUNTIME_DRIVER modules with runtime memory protection enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19235 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-14 08:55:46 +01:00
/** @file
Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
BaseTools: Replace BSD License with BSD+Patent License https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2019-04-04 01:03:11 +02:00
SPDX-License-Identifier: BSD-2-Clause-Patent
BaseTools RVCT: use scatter file to enforce minimum section alignment Up until SVN r18540, GenFw created invalid PE/COFF binaries for the ARM architecture, by allowing PE/COFF .data sections to appear at offsets that were not aligned to the global PE/COFF section alignment. The reason for this was that the relocation metadata emitted by RVCT's armlink only contains dynamic absolute relocations, so it is impossible to recalculate relative relocations between .text and .data, and so the relative offset between the two needs to be preserved. Since r18540, we do align .data to the PE/COFF section alignment, resulting in potentially corrupt PE/COFF binaries unless .data happens to appear at a 32-byte aligned offset. So let's introduce a RVCT scatter file that sets this alignment for the ELF .data section (and subsequent .bss section). At the same time, set the start offset to 0x220 bytes (which is the size of our 32-bit PE/COFF header) so that the memory layouts are identical between ELF and PE/COFF. Also add a 4 KB aligned version that can be used to build DXE_RUNTIME_DRIVER modules with runtime memory protection enabled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19235 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-14 08:55:46 +01:00
**/
REGION 0x1000 RELOC {
ER_RO +0 ALIGN 4096 {
* (+RO)
}
ER_RW +0 ALIGN 4096 {
* (+RW)
}
ER_ZI +0 {
* (+ZI)
}
}