2011-02-02 23:35:30 +01:00
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Chipset/ArmV7.h>
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#include <Library/ArmLib.h>
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#include <Library/BaseLib.h>
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#include <Library/IoLib.h>
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#include "ArmV7Lib.h"
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#include "ArmLibPrivate.h"
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VOID
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EFIAPI
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ArmSetupSmpNonSecure (
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IN UINTN CoreId
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)
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{
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INTN scu_base;
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ArmSetAuxCrBit (A9_FEATURE_SMP);
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if (CoreId == 0) {
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scu_base = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32(scu_base + SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32(scu_base + SCU_SSACR_OFFSET, 0xfff);
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}
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}
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VOID
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EFIAPI
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ArmInvalidScu (
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VOID
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)
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{
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INTN scu_base;
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scu_base = ArmGetScuBaseAddress();
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2011-06-03 11:18:48 +02:00
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// Invalidate all: write -1 to SCU Invalidate All register
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2011-02-02 23:35:30 +01:00
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MmioWrite32(scu_base + SCU_INVALL_OFFSET, 0xffffffff);
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2011-06-03 11:18:48 +02:00
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// Enable SCU
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2011-02-02 23:35:30 +01:00
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MmioWrite32(scu_base + SCU_CONTROL_OFFSET, 0x1);
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}
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