mirror of https://github.com/acidanthera/audk.git
90 lines
4.2 KiB
C
90 lines
4.2 KiB
C
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/** @file HDLcd.h
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _HDLCD_H_
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#define _HDLCD_H_
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//
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// HDLCD Controller Register Offsets
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//
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#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
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#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
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#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
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#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
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#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
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#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
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#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
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#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
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#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
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#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
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#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
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#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
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#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
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#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
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#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
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#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
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#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
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#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
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#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
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#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
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#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
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#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
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#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
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#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
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//
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// HDLCD Values of registers
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//
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// HDLCD Interrupt mask, clear and status register
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#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
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#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
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#define HDLCD_SYNC BIT2 /* Vertical sync */
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#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
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// CLCD_CONTROL Control register
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#define HDLCD_DISABLE 0
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#define HDLCD_ENABLE BIT0
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// Bus Options
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#define HDLCD_BURST_1 BIT0
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#define HDLCD_BURST_2 BIT1
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#define HDLCD_BURST_4 BIT2
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#define HDLCD_BURST_8 BIT3
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#define HDLCD_BURST_16 BIT4
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// Polarities - HIGH
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#define HDLCD_VSYNC_HIGH BIT0
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#define HDLCD_HSYNC_HIGH BIT1
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#define HDLCD_DATEN_HIGH BIT2
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#define HDLCD_DATA_HIGH BIT3
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#define HDLCD_PXCLK_HIGH BIT4
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// Polarities - LOW (for completion and for ease of understanding the hardware settings)
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#define HDLCD_VSYNC_LOW 0
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#define HDLCD_HSYNC_LOW 0
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#define HDLCD_DATEN_LOW 0
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#define HDLCD_DATA_LOW 0
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#define HDLCD_PXCLK_LOW 0
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// Pixel Format
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#define HDLCD_LITTLE_ENDIAN (0 << 31)
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#define HDLCD_BIG_ENDIAN (1 << 31)
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// Number of bytes per pixel
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#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
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#endif /* _HDLCD_H_ */
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