mirror of https://github.com/acidanthera/audk.git
460 lines
13 KiB
C
460 lines
13 KiB
C
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/*++
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Copyright (c) 2005, Intel Corporation
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All rights reserved. This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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PcatPciRootBridgeIo.c
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Abstract:
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EFI PC AT PCI Root Bridge Io Protocol
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Revision History
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--*/
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#include "PcatPciRootBridge.h"
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#include "pci22.h"
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#include "SalProc.h"
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#include EFI_GUID_DEFINITION (SalSystemTable)
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//
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// Might be good to put this in an include file, but people may start
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// using it! They should always access the EFI abstraction that is
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// contained in this file. Just a little information hiding.
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//
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#define PORT_TO_MEM(_Port) ( ((_Port) & 0xffffffffffff0000) | (((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff) )
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//
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// Macro's with casts make this much easier to use and read.
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//
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#define PORT_TO_MEM8(_Port) (*(UINT8 *)(PORT_TO_MEM(_Port)))
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#define PORT_TO_MEM16(_Port) (*(UINT16 *)(PORT_TO_MEM(_Port)))
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#define PORT_TO_MEM32(_Port) (*(UINT32 *)(PORT_TO_MEM(_Port)))
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#define EFI_PCI_ADDRESS_IA64(_seg, _bus,_dev,_func,_reg) \
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( (UINT64) ( (((UINTN)_seg) << 24) + (((UINTN)_bus) << 16) + (((UINTN)_dev) << 11) + (((UINTN)_func) << 8) + ((UINTN)_reg)) )
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//
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// Local variables for performing SAL Proc calls
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//
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static PLABEL mSalProcPlabel;
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static CALL_SAL_PROC mGlobalSalProc;
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EFI_STATUS
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PcatRootBridgeIoIoRead (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 UserAddress,
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IN UINTN Count,
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IN OUT VOID *UserBuffer
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)
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{
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PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
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UINTN InStride;
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UINTN OutStride;
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UINTN AlignMask;
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UINTN Address;
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PTR Buffer;
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UINT16 Data16;
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UINT32 Data32;
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if ( UserBuffer == NULL ) {
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return EFI_INVALID_PARAMETER;
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}
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
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Address = (UINTN) UserAddress;
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Buffer.buf = (UINT8 *)UserBuffer;
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if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
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return EFI_INVALID_PARAMETER;
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}
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if (Width < 0 || Width >= EfiPciWidthMaximum) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Width & 0x03) == EfiPciWidthUint64) {
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return EFI_INVALID_PARAMETER;
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}
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AlignMask = (1 << (Width & 0x03)) - 1;
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if ( Address & AlignMask ) {
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return EFI_INVALID_PARAMETER;
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}
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InStride = 1 << (Width & 0x03);
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OutStride = InStride;
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if (Width >=EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
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InStride = 0;
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}
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if (Width >=EfiPciWidthFillUint8 && Width <= EfiPciWidthFillUint64) {
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OutStride = 0;
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}
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Width = Width & 0x03;
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Address += PrivateData->PhysicalIoBase;
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//
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// Loop for each iteration and move the data
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//
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switch (Width) {
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case EfiPciWidthUint8:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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*Buffer.ui8 = PORT_TO_MEM8(Address);
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MEMORY_FENCE();
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}
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break;
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case EfiPciWidthUint16:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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if (Buffer.ui & 0x1) {
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Data16 = PORT_TO_MEM16(Address);
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*Buffer.ui8 = (UINT8)(Data16 & 0xff);
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*(Buffer.ui8+1) = (UINT8)((Data16 >> 8) & 0xff);
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} else {
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*Buffer.ui16 = PORT_TO_MEM16(Address);
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}
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MEMORY_FENCE();
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}
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break;
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case EfiPciWidthUint32:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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if (Buffer.ui & 0x3) {
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Data32 = PORT_TO_MEM32(Address);
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*Buffer.ui8 = (UINT8)(Data32 & 0xff);
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*(Buffer.ui8+1) = (UINT8)((Data32 >> 8) & 0xff);
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*(Buffer.ui8+2) = (UINT8)((Data32 >> 16) & 0xff);
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*(Buffer.ui8+3) = (UINT8)((Data32 >> 24) & 0xff);
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} else {
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*Buffer.ui32 = PORT_TO_MEM32(Address);
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}
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MEMORY_FENCE();
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}
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break;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PcatRootBridgeIoIoWrite (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 UserAddress,
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IN UINTN Count,
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IN OUT VOID *UserBuffer
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)
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{
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PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
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UINTN InStride;
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UINTN OutStride;
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UINTN AlignMask;
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UINTN Address;
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PTR Buffer;
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UINT16 Data16;
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UINT32 Data32;
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if ( UserBuffer == NULL ) {
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return EFI_INVALID_PARAMETER;
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}
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
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Address = (UINTN) UserAddress;
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Buffer.buf = (UINT8 *)UserBuffer;
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if ( Address < PrivateData->IoBase || Address > PrivateData->IoLimit ) {
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return EFI_INVALID_PARAMETER;
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}
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if (Width < 0 || Width >= EfiPciWidthMaximum) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Width & 0x03) == EfiPciWidthUint64) {
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return EFI_INVALID_PARAMETER;
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}
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AlignMask = (1 << (Width & 0x03)) - 1;
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if ( Address & AlignMask ) {
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return EFI_INVALID_PARAMETER;
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}
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InStride = 1 << (Width & 0x03);
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OutStride = InStride;
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if (Width >=EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
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InStride = 0;
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}
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if (Width >=EfiPciWidthFillUint8 && Width <= EfiPciWidthFillUint64) {
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OutStride = 0;
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}
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Width = Width & 0x03;
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Address += PrivateData->PhysicalIoBase;
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//
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// Loop for each iteration and move the data
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//
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switch (Width) {
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case EfiPciWidthUint8:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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PORT_TO_MEM8(Address) = *Buffer.ui8;
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MEMORY_FENCE();
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}
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break;
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case EfiPciWidthUint16:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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if (Buffer.ui & 0x1) {
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Data16 = *Buffer.ui8;
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Data16 = Data16 | (*(Buffer.ui8+1) << 8);
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PORT_TO_MEM16(Address) = Data16;
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} else {
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PORT_TO_MEM16(Address) = *Buffer.ui16;
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}
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MEMORY_FENCE();
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}
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break;
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case EfiPciWidthUint32:
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for (; Count > 0; Count--, Buffer.buf += OutStride, Address += InStride) {
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MEMORY_FENCE();
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if (Buffer.ui & 0x3) {
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Data32 = *Buffer.ui8;
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Data32 = Data32 | (*(Buffer.ui8+1) << 8);
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Data32 = Data32 | (*(Buffer.ui8+2) << 16);
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Data32 = Data32 | (*(Buffer.ui8+3) << 24);
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PORT_TO_MEM32(Address) = Data32;
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} else {
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PORT_TO_MEM32(Address) = *Buffer.ui32;
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}
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MEMORY_FENCE();
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}
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break;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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PcatRootBridgeIoGetIoPortMapping (
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OUT EFI_PHYSICAL_ADDRESS *IoPortMapping,
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OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping
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)
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/*++
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Get the IO Port Map from the SAL System Table.
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--*/
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{
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SAL_SYSTEM_TABLE_ASCENDING_ORDER *SalSystemTable;
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SAL_ST_MEMORY_DESCRIPTOR_ENTRY *SalMemDesc;
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EFI_STATUS Status;
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//
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// On all Itanium architectures, bit 63 is the I/O bit for performming Memory Mapped I/O operations
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//
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*MemoryPortMapping = 0x8000000000000000;
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Status = EfiLibGetSystemConfigurationTable(&gEfiSalSystemTableGuid, &SalSystemTable);
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if (EFI_ERROR(Status)) {
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return EFI_NOT_FOUND;
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}
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//
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// BugBug: Add code to test checksum on the Sal System Table
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//
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if (SalSystemTable->Entry0.Type != 0) {
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return EFI_UNSUPPORTED;
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}
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mSalProcPlabel.ProcEntryPoint = SalSystemTable->Entry0.SalProcEntry;
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mSalProcPlabel.GP = SalSystemTable->Entry0.GlobalDataPointer;
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mGlobalSalProc = (CALL_SAL_PROC)&mSalProcPlabel.ProcEntryPoint;
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//
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// The SalSystemTable pointer includes the Type 0 entry.
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// The SalMemDesc is Type 1 so it comes next.
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//
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SalMemDesc = (SAL_ST_MEMORY_DESCRIPTOR_ENTRY *)(SalSystemTable + 1);
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while (SalMemDesc->Type == SAL_ST_MEMORY_DESCRIPTOR) {
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if (SalMemDesc->MemoryType == SAL_IO_PORT_MAPPING) {
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*IoPortMapping = SalMemDesc->PhysicalMemoryAddress;
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*IoPortMapping |= 0x8000000000000000;
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return EFI_SUCCESS;
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}
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SalMemDesc++;
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}
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return EFI_UNSUPPORTED;
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}
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EFI_STATUS
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PcatRootBridgeIoPciRW (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN BOOLEAN Write,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 UserAddress,
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IN UINTN Count,
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IN OUT UINT8 *UserBuffer
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)
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{
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PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
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UINTN AlignMask;
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UINTN InStride;
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UINTN OutStride;
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UINT64 Address;
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DEFIO_PCI_ADDR *Defio;
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PTR Buffer;
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UINT32 Data32;
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UINT16 Data16;
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rArg Return;
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if (Width < 0 || Width >= EfiPciWidthMaximum) {
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return EFI_INVALID_PARAMETER;
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}
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if ((Width & 0x03) == EfiPciWidthUint64) {
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return EFI_INVALID_PARAMETER;
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}
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AlignMask = (1 << (Width & 0x03)) - 1;
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if ( UserAddress & AlignMask ) {
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return EFI_INVALID_PARAMETER;
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}
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InStride = 1 << (Width & 0x03);
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OutStride = InStride;
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if (Width >=EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
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InStride = 0;
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}
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if (Width >=EfiPciWidthFillUint8 && Width <= EfiPciWidthFillUint64) {
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OutStride = 0;
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}
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Width = Width & 0x03;
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Defio = (DEFIO_PCI_ADDR *)&UserAddress;
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if ((Defio->Function > PCI_MAX_FUNC) || (Defio->Device > PCI_MAX_DEVICE)) {
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return EFI_UNSUPPORTED;
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}
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Buffer.buf = (UINT8 *)UserBuffer;
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
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Address = EFI_PCI_ADDRESS_IA64(
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This->SegmentNumber,
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Defio->Bus,
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Defio->Device,
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Defio->Function,
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Defio->Register
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);
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//
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// PCI Config access are all 32-bit alligned, but by accessing the
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// CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
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// are possible on PCI.
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//
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// SalProc takes care of reading the proper register depending on stride
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//
|
||
|
|
|
||
|
|
EfiAcquireLock(&PrivateData->PciLock);
|
||
|
|
|
||
|
|
while (Count) {
|
||
|
|
|
||
|
|
if(Write) {
|
||
|
|
|
||
|
|
if (Buffer.ui & 0x3) {
|
||
|
|
Data32 = (*(Buffer.ui8+0) << 0);
|
||
|
|
Data32 |= (*(Buffer.ui8+1) << 8);
|
||
|
|
Data32 |= (*(Buffer.ui8+2) << 16);
|
||
|
|
Data32 |= (*(Buffer.ui8+3) << 24);
|
||
|
|
} else {
|
||
|
|
Data32 = *Buffer.ui32;
|
||
|
|
}
|
||
|
|
|
||
|
|
Return.p0 = -3;
|
||
|
|
Return = mGlobalSalProc((UINT64) SAL_PCI_CONFIG_WRITE,
|
||
|
|
Address, 1 << Width, Data32, 0, 0, 0, 0);
|
||
|
|
|
||
|
|
if(Return.p0) {
|
||
|
|
EfiReleaseLock(&PrivateData->PciLock);
|
||
|
|
return EFI_UNSUPPORTED;
|
||
|
|
}
|
||
|
|
|
||
|
|
} else {
|
||
|
|
|
||
|
|
Return.p0 = -3;
|
||
|
|
Return = mGlobalSalProc((UINT64) SAL_PCI_CONFIG_READ,
|
||
|
|
Address, 1 << Width, 0, 0, 0, 0, 0);
|
||
|
|
|
||
|
|
if(Return.p0) {
|
||
|
|
EfiReleaseLock(&PrivateData->PciLock);
|
||
|
|
return EFI_UNSUPPORTED;
|
||
|
|
}
|
||
|
|
|
||
|
|
switch (Width) {
|
||
|
|
case EfiPciWidthUint8:
|
||
|
|
*Buffer.ui8 = (UINT8)Return.p1;
|
||
|
|
break;
|
||
|
|
case EfiPciWidthUint16:
|
||
|
|
if (Buffer.ui & 0x1) {
|
||
|
|
Data16 = (UINT16)Return.p1;
|
||
|
|
*(Buffer.ui8 + 0) = Data16 & 0xff;
|
||
|
|
*(Buffer.ui8 + 1) = (Data16 >> 8) & 0xff;
|
||
|
|
} else {
|
||
|
|
*Buffer.ui16 = (UINT16)Return.p1;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case EfiPciWidthUint32:
|
||
|
|
if (Buffer.ui & 0x3) {
|
||
|
|
Data32 = (UINT32)Return.p1;
|
||
|
|
*(Buffer.ui8 + 0) = (UINT8)(Data32 & 0xff);
|
||
|
|
*(Buffer.ui8 + 1) = (UINT8)((Data32 >> 8) & 0xff);
|
||
|
|
*(Buffer.ui8 + 2) = (UINT8)((Data32 >> 16) & 0xff);
|
||
|
|
*(Buffer.ui8 + 3) = (UINT8)((Data32 >> 24) & 0xff);
|
||
|
|
} else {
|
||
|
|
*Buffer.ui32 = (UINT32)Return.p1;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
Address += InStride;
|
||
|
|
Buffer.buf += OutStride;
|
||
|
|
Count -= 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
EfiReleaseLock(&PrivateData->PciLock);
|
||
|
|
|
||
|
|
return EFI_SUCCESS;
|
||
|
|
}
|
||
|
|
|
||
|
|
EFI_STATUS
|
||
|
|
ScanPciRootBridgeForRoms(
|
||
|
|
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
|
||
|
|
)
|
||
|
|
|
||
|
|
{
|
||
|
|
return EFI_UNSUPPORTED;
|
||
|
|
}
|