2015-01-12 10:37:20 +01:00
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/*++
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2015-11-13 03:38:08 +01:00
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Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
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2015-01-12 10:37:20 +01:00
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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GlobalNvsArea.h
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Abstract:
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Definition of the global NVS area protocol. This protocol
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publishes the address and format of a global ACPI NVS buffer used as a communications
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buffer between SMM code and ASL code.
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The format is derived from the ACPI reference code, version 0.95.
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Note: Data structures defined in this protocol are not naturally aligned.
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**/
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#ifndef _GLOBAL_NVS_AREA_H_
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#define _GLOBAL_NVS_AREA_H_
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//
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// Includes
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//
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#define GLOBAL_NVS_DEVICE_ENABLE 1
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#define GLOBAL_NVS_DEVICE_DISABLE 0
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//
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// Forward reference for pure ANSI compatibility
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//
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//EFI_FORWARD_DECLARATION (EFI_GLOBAL_NVS_AREA_PROTOCOL);
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//
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// Global NVS Area Protocol GUID
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//
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#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
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{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
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//
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// Revision id - Added TPM related fields
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//
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#define GLOBAL_NVS_AREA_RIVISION_1 1
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//
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// Extern the GUID for protocol users.
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//
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extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
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//
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// Global NVS Area definition
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//
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#pragma pack (1)
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typedef struct {
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//
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// Miscellaneous Dynamic Values, the definitions below need to be matched
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// GNVS definitions in Platform.ASL
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//
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UINT16 OperatingSystem; // 00
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UINT8 SmiFunction; // 02 SMI function call via IO Trap
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UINT8 SmiParameter0; // 03
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UINT8 SmiParameter1; // 04
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UINT8 SciFunction; // 05 SCI function call via _L00
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UINT8 SciParameter0; // 06
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UINT8 SciParameter1; // 07
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UINT8 GlobalLock; // 08 Global lock function call
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UINT8 LockParameter0; // 09
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UINT8 LockParameter1; // 10
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UINT32 Port80DebugValue; // 11
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UINT8 LidState; // 15 Open = 1
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UINT8 PowerState; // 16 AC = 1
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UINT8 DebugState; // 17
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//
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// Thermal Policy Values
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//
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UINT8 EnableThermalOffset; // 18 ThermalOffset for KSC
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UINT8 Reserved1; // 19
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UINT8 Reserved2; // 20
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UINT8 PassiveThermalTripPoint; // 21
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UINT8 PassiveTc1Value; // 22
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UINT8 PassiveTc2Value; // 23
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UINT8 PassiveTspValue; // 24
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UINT8 CriticalThermalTripPoint; // 25
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2015-05-27 07:47:57 +02:00
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UINT8 EnableDigitalThermalSensor; // 26
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2015-01-12 10:37:20 +01:00
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UINT8 BspDigitalThermalSensorTemperature; // 27 Temperature of BSP
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UINT8 ApDigitalThermalSensorTemperature; // 28 Temperature of AP
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UINT8 DigitalThermalSensorSmiFunction; // 29 SMI function call via DTS IO Trap
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//
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// Battery Support Values
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//
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UINT8 NumberOfBatteries; // 30
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UINT8 BatteryCapacity0; // 31 Battery 0 Stored Capacity
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UINT8 BatteryCapacity1; // 32 Battery 1 Stored Capacity
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UINT8 BatteryCapacity2; // 33 Battery 2 Stored Capacity
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UINT8 BatteryStatus0; // 34 Battery 0 Stored Status
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UINT8 BatteryStatus1; // 35 Battery 1 Stored Status
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UINT8 BatteryStatus2; // 36 Battery 2 Stored Status
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// NOTE: Do NOT Change the Offset of Revision Field
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UINT8 Revision; // 37 Revision of the structure EFI_GLOBAL_NVS_AREA
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UINT8 Reserved3[2]; // 38:39
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//
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// Processor Configuration Values
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//
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UINT8 ApicEnable; // 40 APIC Enabled by SBIOS (APIC Enabled = 1)
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UINT8 LogicalProcessorCount; // 41 Processor Count Enabled (MP Enabled != 0)
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UINT8 CurentPdcState0; // 42 PDC settings, Processor 0
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UINT8 CurentPdcState1; // 43 PDC settings, Processor 1
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UINT8 MaximumPpcState; // 44 Maximum PPC state
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UINT32 PpmFlags; // 45:48 PPM configuration flags, same as CFGD
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UINT8 Reserved4[1]; // 49
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//
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// SIO Configuration Values
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//
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UINT8 DockedSioPresent; // 50 Dock SIO Present
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UINT8 DockComA; // 51 COM A Port
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UINT8 DockComB; // 52 COM B Port
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UINT8 LptP; // 53 LPT Port
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UINT8 DockFdc; // 54 FDC Port
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UINT8 OnboardCom; // 55 Onboard COM Port
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UINT8 OnboardComCir; // 56 Onboard COM CIR Port
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UINT8 WPCN381U; // 57
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UINT8 NPCE791x; // 58
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UINT8 Reserved5[1]; // 59
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//
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// Internal Graphics Device Values
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//
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UINT8 IgdState; // 60 IGD State (Primary Display = 1)
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UINT8 DisplayToggleList; // 61 Display Toggle List Selection
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UINT8 CurrentDeviceList; // 62 Current Attached Device List
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UINT8 PreviousDeviceList; // 63 Previous Attached Device List
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UINT16 CurrentDisplayState; // 64 Current Display State
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UINT16 NextDisplayState; // 66 Next Display State
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UINT16 SetDisplayState; // 68 Set Display State
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UINT8 NumberOfValidDeviceId; // 70 Number of Valid Device IDs
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UINT32 DeviceId1; // 71 Device ID 1
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UINT32 DeviceId2; // 75 Device ID 2
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UINT32 DeviceId3; // 79 Device ID 3
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UINT32 DeviceId4; // 83 Device ID 4
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UINT32 DeviceId5; // 87 Device ID 5
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UINT32 AKsv0; // 91:94 First four bytes of AKSV (manufacturing mode)
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UINT8 AKsv1; // 95 Fifth byte of AKSV (manufacturing mode
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UINT8 Reserved6[7]; // 96:102
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//
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// Backlight Control Values
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//
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UINT8 BacklightControlSupport; // 103 Backlight Control Support
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UINT8 BrightnessPercentage; // 104 Brightness Level Percentage
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//
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// Ambient Light Sensor Values
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//
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UINT8 AlsEnable; // 105 Ambient Light Sensor Enable
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UINT8 AlsAdjustmentFactor; // 106 Ambient Light Adjusment Factor
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UINT8 LuxLowValue; // 107 LUX Low Value
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UINT8 LuxHighValue; // 108 LUX High Value
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UINT8 Reserved7[1]; // 109
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//
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// Extended Mobile Access Values
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//
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UINT8 EmaEnable; // 110 EMA Enable
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UINT16 EmaPointer; // 111 EMA Pointer
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UINT16 EmaLength; // 113 EMA Length
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UINT8 Reserved8[1]; // 115
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//
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// Mobile East Fork Values
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//
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UINT8 MefEnable; // 116 Mobile East Fork Enable
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//
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// PCIe Dock Status
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//
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UINT8 PcieDockStatus; // 117 PCIe Dock Status
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UINT8 Reserved9[2]; // 118:119
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//
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// TPM Registers
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//
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UINT8 TpmPresent; // 120 TPM Present
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UINT8 TpmEnable; // 121 TPM Enable
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UINT8 MorData; // 122 Memory Overwrite Request Data
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UINT8 TcgParamter; // 123 Used for save the Mor and/or physical presence paramter
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UINT32 PPResponse; // 124 Physical Presence request operation response
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UINT8 PPRequest; // 128 Physical Presence request operation
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UINT8 LastPPRequest; // 129 Last Physical Presence request operation
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//
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// SATA Values
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//
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UINT8 GtfTaskFileBufferPort0[7]; // 130 GTF Task File Buffer for Port 0
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UINT8 GtfTaskFileBufferPort2[7]; // 137 GTF Task File Buffer for Port 2
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UINT8 IdeMode; // 144 IDE Mode (Compatible\Enhanced)
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UINT8 GtfTaskFileBufferPort1[7]; // 145:151 GTF Task File Buffer for Port 1
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UINT8 Reserved111[10]; // 152:161
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UINT64 BootTimeLogAddress; // 162:169 Boot Time Log Table Address
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UINT32 IgdOpRegionAddress; // 170 IGD OpRegion Starting Address
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UINT8 IgdBootType; // 174 IGD Boot Type CMOS option
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UINT8 IgdPanelType; // 175 IGD Panel Type CMOs option
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UINT8 IgdTvFormat; // 176 IGD TV Format CMOS option
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UINT8 IgdTvMinor; // 177 IGD TV Minor Format CMOS option
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UINT8 IgdPanelScaling; // 178 IGD Panel Scaling
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UINT8 IgdBlcConfig; // 179 IGD BLC Configuration
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UINT8 IgdBiaConfig; // 180 IGD BIA Configuration
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UINT8 IgdSscConfig; // 181 IGD SSC Configuration
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UINT8 Igd409; // 182 IGD 0409 Modified Settings Flag
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UINT8 Igd509; // 183 IGD 0509 Modified Settings Flag
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UINT8 Igd609; // 184 IGD 0609 Modified Settings Flag
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UINT8 Igd709; // 185 IGD 0709 Modified Settings Flag
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UINT8 IgdPowerConservation; // 186 IGD Power Conservation Feature Flag
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UINT8 IgdDvmtMemSize; // 187 IGD DVMT Memory Size
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UINT8 IgdFunc1Enable; // 188 IGD Function 1 Enable
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UINT8 IgdHpllVco; // 189 HPLL VCO
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UINT32 NextStateDid1; // 190 Next state DID1 for _DGS
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UINT32 NextStateDid2; // 194 Next state DID2 for _DGS
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UINT32 NextStateDid3; // 198 Next state DID3 for _DGS
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UINT32 NextStateDid4; // 202 Next state DID4 for _DGS
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UINT32 NextStateDid5; // 206 Next state DID5 for _DGS
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UINT32 NextStateDid6; // 210 Next state DID6 for _DGS
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UINT32 NextStateDid7; // 214 Next state DID7 for _DGS
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UINT32 NextStateDid8; // 218 Next state DID8 for _DGS
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UINT8 IgdSciSmiMode; // 222 GMCH SMI/SCI mode (0=SCI)
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UINT8 IgdPAVP; // 223 IGD PAVP data
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UINT8 IgdSelfRefresh; // 224 IGD Self Refresh
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UINT8 PcieOSCControl; // 225 PCIE OSC Control
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UINT8 NativePCIESupport; // 226 Native PCI Express Support
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//
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// USB Sideband Deferring Support
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//
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UINT8 HostAlertVector; // 227 GPE vector used for HOST_ALERT
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UINT8 HostAlertPio; // 228 PIO of USB device used for HOST_ALERT
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UINT8 Reserved112[27]; // 229
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UINT32 NvIgOpRegionAddress; // 256 NVIG support
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UINT32 NvHmOpRegionAddress; // 260 NVHM support
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UINT32 ApXmOpRegionAddress; // 264 AMDA support
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UINT32 DeviceId6; // 268 Device ID 6
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UINT32 DeviceId7; // 272 Device ID 7
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UINT32 DeviceId8; // 276 Device ID 8
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UINT32 EndpointBaseAddress; // 280 PEG Endpoint PCIe Base Address
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UINT32 CapStrPresence; // 284 PEG Endpoint Capability Structure Presence
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UINT32 EndpointPcieCapBaseAddress; // 288 PEG Endpoint PCIe Capability Structure Base Address
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UINT32 EndpointVcCapBaseAddress; // 292 PEG Endpoint Virtual Channel Capability Structure Base Address
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UINT32 XPcieCfgBaseAddress; // 296 Any Device's PCIe Config Space Base Address
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UINT32 OccupiedBuses1; // 300 Occupied Buses from 0 to 31
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UINT32 OccupiedBuses2; // 304 Occupied Buses from 32 to 63
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UINT32 OccupiedBuses3; // 308 Occupied Buses from 64 to 95
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UINT32 OccupiedBuses4; // 312 Occupied Buses from 96 to 127
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UINT32 OccupiedBuses5; // 316 Occupied Buses from 128 to 159
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UINT32 OccupiedBuses6; // 320 Occupied Buses from 160 to 191
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UINT32 OccupiedBuses7; // 324 Occupied Buses from 192 to 223
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UINT32 OccupiedBuses8; // 328 Occupied Buses from 224 to 255
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UINT8 UartSelection; // 332 UART Interface Selection 0: Internal; 1: SIO
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UINT8 PcuUart1Enable; // 333 PCU UART 1 Enabled
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UINT8 PcuUart2Enable; // 334 PCU UART 2 Enabled
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UINT32 LPEBar0; // 335~338 LPE Bar0
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UINT32 LPEBar1; // 339~342 LPE Bar1
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UINT32 LPEBar2; // 343~346 LPE Bar2
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UINT8 AcSetup; // 347 For Ac Powered Config option - IST applet
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UINT8 BatterySetup; // 348 For Battery Powered Config option - IST applet
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UINT8 PlatformFlavor; // 349 0:unknown 1: Mobile; 2: desktop
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UINT8 Reserved113[1]; // 350
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UINT8 IsctReserve; // 351 ISCT / AOAC Configuration
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UINT8 XhciMode; // 352 xHCI mode
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UINT8 PmicEnable; // 353 PMIC enable
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UINT8 LpeEnable; // 354 LPE enable
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UINT32 ISPAddr; // 355 ISP Base address
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UINT8 ISPDevSel; // 359 ISP device enabled selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
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//
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// Lpss controllers
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//
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UINT32 PCIBottomAddress; //360 ((4+8+6)*4+2)*4=296
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UINT32 PCITopAddress; //364
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UINT32 LDMA1Addr; // 368
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UINT32 LDMA1Len; // 372
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UINT32 LDMA11Addr; // 376
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UINT32 LDMA11Len; // 380
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UINT32 PWM1Addr; // 384 PWM1
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UINT32 PWM1Len; // 388
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UINT32 PWM11Addr; // 392
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UINT32 PWM11Len; // 396
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UINT32 PWM2Addr; // 400 PWM2
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UINT32 PWM2Len; // 404
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UINT32 PWM21Addr; // 408
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UINT32 PWM21Len; // 412
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UINT32 UART1Addr; // 416 UART1
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UINT32 UART1Len; // 420
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UINT32 UART11Addr; // 424 UART1
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UINT32 UART11Len; // 428
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UINT32 UART2Addr; // 432 UART2
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UINT32 UART2Len; // 436
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UINT32 UART21Addr; // 440 UART2
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UINT32 UART21Len; // 444
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UINT32 SPIAddr; // 448 SPI
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UINT32 SPILen; // 452
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UINT32 SPI1Addr; // 456
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UINT32 SPI1Len; // 460
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UINT32 LDMA2Addr; // 464
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UINT32 LDMA2Len; // 468
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UINT32 LDMA21Addr; // 472
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UINT32 LDMA21Len; // 476
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UINT32 I2C1Addr; // 480 I2C1
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UINT32 I2C1Len; // 484
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UINT32 I2C11Addr; // 488 I2C1
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UINT32 I2C11Len; // 492
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UINT32 I2C2Addr; // 496 I2C2
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UINT32 I2C2Len; // 500
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UINT32 I2C21Addr; // 504 I2C2
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UINT32 I2C21Len; // 508
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UINT32 I2C3Addr; // 512 I2C3
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UINT32 I2C3Len; // 516
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UINT32 I2C31Addr; // 520 I2C3
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UINT32 I2C31Len; // 524
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UINT32 I2C4Addr; // 528 I2C4
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UINT32 I2C4Len; // 532
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UINT32 I2C41Addr; // 536 I2C4
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UINT32 I2C41Len; // 540
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UINT32 I2C5Addr; // 544 I2C5
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UINT32 I2C5Len; // 548
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UINT32 I2C51Addr; // 552 I2C5
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UINT32 I2C51Len; // 556
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UINT32 I2C6Addr; // 560 I2C6
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UINT32 I2C6Len; // 564
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UINT32 I2C61Addr; // 566 I2C6
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UINT32 I2C61Len; // 570
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UINT32 I2C7Addr; // 574 I2C7
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UINT32 I2C7Len; // 578
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UINT32 I2C71Addr; // 582 I2C7
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UINT32 I2C71Len; // 586
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//
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// Scc controllers
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//
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UINT32 eMMCAddr; // 590 EMMC
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UINT32 eMMCLen; // 594
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UINT32 eMMC1Addr; // 598
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UINT32 eMMC1Len; // 602
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UINT32 SDIOAddr; // 606 SDIO
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UINT32 SDIOLen; // 610
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UINT32 SDIO1Addr; // 614
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UINT32 SDIO1Len; // 618
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UINT32 SDCardAddr; // 622 SDCard
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UINT32 SDCardLen; // 626
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UINT32 SDCard1Addr; // 630
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UINT32 SDCard1Len; // 636
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UINT32 MipiHsiAddr; // 640 MIPI-HSI
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UINT32 MipiHsiLen; // 644
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UINT32 MipiHsi1Addr; // 648
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UINT32 MipiHsi1Len; // 652
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UINT8 SdCardRemovable; // 656 reserve offset upto 658
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UINT8 HideLPSSDevices; // 657 Hide unsupported LPSS devices when in ACPI mode
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UINT8 ReservedO; // 658 OS Selection
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UINT8 Reserved00; // 659
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UINT8 Reserved01; // 660
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UINT8 Reserved02; // 661
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UINT8 Reserved03; // 662
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UINT8 Reserved04; // 663
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UINT8 Reserved05; // 664
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UINT8 Reserved06; // 665
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UINT8 Reserved07; // 666
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UINT8 Reserved08; // 667
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UINT8 Reserved09; // 668
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UINT8 Reserved0A; // 669
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UINT32 Reserved0B; // 670
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UINT32 Reserved0C; // 674
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UINT32 Reserved0D; // 678
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UINT32 Reserved0E; // 682
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UINT32 Reserved0F; // 686
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UINT32 Reserved10; // 690
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UINT32 Reserved11; // 694
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UINT32 Reserved12; // 698
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UINT32 Reserved13; // 702
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UINT32 Reserved14; // 706
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UINT32 Reserved15; // 710
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UINT32 Reserved16; // 714
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UINT8 Reserved17;
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UINT32 Reserved18;
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UINT32 Reserved19;
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UINT32 Reserved1A;
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UINT32 Reserved1B;
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UINT32 Reserved1C;
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UINT8 Reserved1D;
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UINT32 Reserved1E;
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UINT32 Reserved1F;
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UINT32 Reserved20;
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UINT32 Reserved21;
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UINT32 Reserved22;
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UINT8 Reserved23;
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UINT8 BatteryChargingSolution; // 761 0-non ULPMC 1-ULPMC
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//
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//101 bytes
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//
|
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UINT8 NFCnSelect; // 762 NFCx Select 1: NFC1 2:NFC2
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UINT8 LpssSccMode; // 763 EMMC device 0-ACPI mode, 1-PCI mode
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UINT32 TPMAddress; // 764
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UINT32 TPMLength; // 768
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UINT8 I2CTouchAddress; // 772 I2C touch address, 0x4B:RVP 0x4A:FFRD
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UINT8 IdleReserve; // 773 0 - disabled 1 - enabled
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UINT8 SDIOMode; // 774 3 - Default 2 - DDR50
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UINT8 emmcVersion; // 775 0 - 4.41 1 - 4.5
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UINT32 BmBound; // 776 BM Bound
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UINT8 FsaStatus; // 780 0 - Fsa is off, 1- Fsa is on
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//
|
|
|
|
|
// Board Id
|
|
|
|
|
// This field is for the ASL code to know whether this board is Baylake or Bayley Bay etc
|
|
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//
|
|
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UINT8 BoardID; // 781
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UINT8 FabID; // 782
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UINT8 OtgMode; // 783 0- OTG disable 1- OTG PCI mode
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UINT8 Stepping; // 784 Stepping
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UINT8 WittEnable; // 785 WITT eanble 0 - disable 1 - enable
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UINT8 SocStepping; // 786 Soc Stepping infomation
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UINT8 AmbientTripPointChange; // 787 DPTF: Controls whether _ATI changes other participant's trip point(enabled/disabled)
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UINT8 UtsEnable; // 788 Uart Test eanble 0 - disable 1 - enable
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UINT8 DptfReserve; // 789
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UINT8 SarEnable; // 790
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UINT8 PssDeveice; // 791 PSS Deveice: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K
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UINT8 EDPV; // 792 Check for eDP display device
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UINT32 DIDX; // 793 Device ID for eDP device
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UINT8 MicrosoftIoT; // (794)JP1 pins are for Microsoft IoT project.
|
2015-11-10 08:47:29 +01:00
|
|
|
UINT8 RtcBattery; // (795) The Flag of RTC Battery Present.
|
2015-01-12 10:37:20 +01:00
|
|
|
} EFI_GLOBAL_NVS_AREA;
|
|
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|
|
#pragma pack ()
|
|
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|
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|
|
|
//
|
|
|
|
|
// Global NVS Area Protocol
|
|
|
|
|
//
|
|
|
|
|
typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
|
|
|
|
|
EFI_GLOBAL_NVS_AREA *Area;
|
|
|
|
|
} EFI_GLOBAL_NVS_AREA_PROTOCOL;
|
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#endif
|
