mirror of https://github.com/acidanthera/audk.git
325 lines
12 KiB
C
325 lines
12 KiB
C
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/** @file
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* Header containing the structure specific to the Xpress-RICH3 PCIe Root Complex
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*
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* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __PCIHOSTBRIDGE_H
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#define __PCIHOSTBRIDGE_H
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#include <PiDxe.h>
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#include "XPressRich3.h"
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Acpi.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/DevicePath.h>
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#include <Protocol/CpuIo2.h>
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#include <Protocol/Metronome.h>
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#define PCI_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_PCI: " txt "\n"))
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#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }
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#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }
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#define PCIE_CONTROL_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Value); }
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#define PCIE_CONTROL_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieControlBaseAddress)+(Add)),1,&Val); }
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/**
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* PCI Root Bridge Device Path (ACPI Device Node + End Node)
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*/
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typedef struct {
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ACPI_HID_DEVICE_PATH Acpi;
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EFI_DEVICE_PATH_PROTOCOL End;
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} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
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typedef enum {
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ResTypeIo = 0,
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ResTypeMem32,
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ResTypePMem32,
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ResTypeMem64,
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ResTypePMem64,
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ResTypeMax
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} PCI_RESOURCE_TYPE;
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#define ACPI_SPECFLAG_PREFETCHABLE 0x06
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#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
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#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
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typedef struct {
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UINT64 Base;
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UINT64 Length;
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UINT64 Alignment;
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} PCI_RESOURCE_ALLOC;
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typedef struct _PCI_HOST_BRIDGE_INSTANCE PCI_HOST_BRIDGE_INSTANCE;
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/**
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* PCI Root Bridge Instance structure
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**/
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typedef struct {
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UINTN Signature;
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EFI_HANDLE Handle;
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PCI_HOST_BRIDGE_INSTANCE *HostBridge;
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//
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// Set Type of memory allocation (could be EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM
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// and EFI_PCI_HOST_BRIDGE_MEM64_DECODE).
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//
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UINT64 MemAllocAttributes;
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PCI_RESOURCE_ALLOC ResAlloc[ResTypeMax];
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UINTN BusStart;
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UINTN BusLength;
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UINT64 Supports;
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UINT64 Attributes;
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EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
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} PCI_ROOT_BRIDGE_INSTANCE;
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/**
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* PCI Host Bridge Instance structure
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**/
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struct _PCI_HOST_BRIDGE_INSTANCE {
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UINTN Signature;
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EFI_HANDLE Handle;
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EFI_HANDLE ImageHandle;
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PCI_ROOT_BRIDGE_INSTANCE *RootBridge;
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//
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// The enumeration cannot be restarted after the process goes into the non initial
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// enumeration phase.
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//
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BOOLEAN CanRestarted;
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EFI_CPU_IO2_PROTOCOL *CpuIo;
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EFI_METRONOME_ARCH_PROTOCOL *Metronome;
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EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
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};
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#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32 ('e', 'h', 's', 't')
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#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('e', '2', 'p', 'b')
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#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) CR (a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
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#define INSTANCE_FROM_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
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/**
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* PCI Host Bridge Resource Allocator Functions
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**/
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EFI_STATUS PciHbRaNotifyPhase (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
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);
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EFI_STATUS PciHbRaGetNextRootBridge (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN OUT EFI_HANDLE *RootBridgeHandle
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);
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EFI_STATUS PciHbRaGetAllocAttributes (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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OUT UINT64 *Attributes
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);
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EFI_STATUS PciHbRaStartBusEnumeration (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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OUT VOID **Configuration
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);
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EFI_STATUS PciHbRaSetBusNumbers (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN VOID *Configuration
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);
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EFI_STATUS PciHbRaSubmitResources (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN VOID *Configuration
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);
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EFI_STATUS PciHbRaGetProposedResources (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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OUT VOID **Configuration
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);
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EFI_STATUS PciHbRaPreprocessController (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
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IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
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);
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/**
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* PCI Root Bridge
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**/
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EFI_STATUS PciRbPollMem (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINT64 Mask,
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IN UINT64 Value,
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IN UINT64 Delay,
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OUT UINT64 *Result
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);
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EFI_STATUS PciRbPollIo (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINT64 Mask,
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IN UINT64 Value,
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IN UINT64 Delay,
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OUT UINT64 *Result
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);
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EFI_STATUS PciRbMemRead (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbMemWrite (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbIoRead (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbIoWrite (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbPciRead (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbPciWrite (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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IN UINTN Count,
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IN OUT VOID *Buffer
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);
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EFI_STATUS PciRbCopyMem (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 DestAddress,
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IN UINT64 SrcAddress,
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IN UINTN Count
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);
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EFI_STATUS PciRbMap (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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);
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EFI_STATUS PciRbUnMap (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN VOID *Mapping
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);
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EFI_STATUS PciRbAllocateBuffer (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_ALLOCATE_TYPE Type,
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IN EFI_MEMORY_TYPE MemoryType,
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IN UINTN Pages,
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IN OUT VOID **HostAddress,
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IN UINT64 Attributes
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);
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EFI_STATUS PciRbFreeBuffer (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN UINTN Pages,
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IN VOID *HostAddress
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);
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EFI_STATUS PciRbFlush (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
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);
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EFI_STATUS PciRbSetAttributes (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN UINT64 Attributes,
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IN OUT UINT64 *ResourceBase,
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IN OUT UINT64 *ResourceLength
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);
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EFI_STATUS PciRbGetAttributes (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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OUT UINT64 *Supports,
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OUT UINT64 *Attributes
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);
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EFI_STATUS PciRbConfiguration (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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OUT VOID **Resources
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);
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/**
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* PCI Root Bridge Functions
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**/
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EFI_STATUS
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PciRbConstructor (
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IN PCI_HOST_BRIDGE_INSTANCE *HostBridge,
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IN UINT32 PciAcpiUid,
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IN UINT64 MemAllocAttributes
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);
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EFI_STATUS
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PciRbDestructor (
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IN PCI_ROOT_BRIDGE_INSTANCE* RootBridge
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);
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EFI_STATUS
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HWPciRbInit (
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IN EFI_CPU_IO2_PROTOCOL *CpuIo
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);
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#endif
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