mirror of https://github.com/acidanthera/audk.git
270 lines
9.0 KiB
C
270 lines
9.0 KiB
C
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/** @file
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* Header containing the structure specific to the Silicon Image I3132 Sata PCI card
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*
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* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __SATASII3132_H
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#define __SATASII3132_H
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#include <PiDxe.h>
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#include <Protocol/AtaPassThru.h>
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#include <Protocol/PciIo.h>
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#include <Library/UefiLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <IndustryStandard/Pci.h>
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#define SATA_SII3132_DEVICE_ID 0x3132
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#define SATA_SII3132_VENDOR_ID 0x1095
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#define SII3132_PORT_SIGNATURE_PMP 0x96690101
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#define SII3132_PORT_SIGNATURE_ATAPI 0xEB140101
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#define SII3132_PORT_SIGNATURE_ATA 0x00000101
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/*
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* Silicon Image SiI3132 Registers
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*/
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#define SII3132_GLOBAL_CONTROL_REG 0x40
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#define SII3132_GLOBAL_FLASHADDR_REG 0x70
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#define SII3132_PORT_STATUS_REG 0x1000
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#define SII3132_PORT_CONTROLSET_REG 0x1000
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#define SII3132_PORT_CONTROLCLEAR_REG 0x1004
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#define SII3132_PORT_INTSTATUS_REG 0x1008
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#define SII3132_PORT_ENABLEINT_REG 0x1010
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#define SII3132_PORT_INTCLEAR_REG 0x1014
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#define SII3132_PORT_32BITACTIVADDR_REG 0x101C
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#define SII3132_PORT_CMDEXECFIFO_REG 0x1020
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#define SII3132_PORT_CMDERROR_REG 0x1024
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#define SII3132_PORT_ERRCOUNTDECODE 0x1040
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#define SII3132_PORT_ERRCOUNTCRC 0x1044
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#define SII3132_PORT_ERRCOUNTHANDSHAKE 0x1048
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#define SII3132_PORT_SLOTSTATUS_REG 0x1800
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#define SII3132_PORT_CMDACTIV_REG 0x1C00
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#define SII3132_PORT_SSTATUS_REG 0x1F04
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#define SII3132_PORT_CONTROL_RESET (1 << 0)
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#define SII3132_PORT_DEVICE_RESET (1 << 1)
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#define SII3132_PORT_CONTROL_INT (1 << 2)
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#define SII3132_PORT_CONTROL_32BITACTIVATION (1 << 10)
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#define SII3132_PORT_STATUS_PORTREADY 0x80000000
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#define SII3132_PORT_INT_CMDCOMPL (1 << 0)
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#define SII3132_PORT_INT_CMDERR (1 << 1)
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#define SII3132_PORT_INT_PORTRDY (1 << 2)
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#define SATA_SII3132_MAXPORT 2
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#define PRB_CTRL_ATA 0x0
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#define PRB_CTRL_PROT_OVERRIDE 0x1
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#define PRB_CTRL_RESTRANSMIT 0x2
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#define PRB_CTRL_EXT_CMD 0x4
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#define PRB_CTRL_RCV 0x8
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#define PRB_CTRL_PKT_READ 0x10
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#define PRB_CTRL_PKT_WRITE 0x20
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#define PRB_CTRL_INT_MASK 0x40
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#define PRB_CTRL_SRST 0x80
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#define PRB_PROT_PACKET 0x01
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#define PRB_PROT_LEGACY_QUEUE 0x02
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#define PRB_PROT_NATIVE_QUEUE 0x04
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#define PRB_PROT_READ 0x08
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#define PRB_PROT_WRITE 0x10
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#define PRB_PROT_TRANSPARENT 0x20
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#define SGE_XCF (1 << 28)
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#define SGE_DRD (1 << 29)
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#define SGE_LNK (1 << 30)
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#define SGE_TRM 0x80000000
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typedef struct _SATA_SI3132_SGE {
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UINT32 DataAddressLow;
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UINT32 DataAddressHigh;
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UINT32 DataCount;
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UINT32 Attributes;
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} SATA_SI3132_SGE;
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typedef struct _SATA_SI3132_FIS {
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UINT8 FisType;
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UINT8 Control;
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UINT8 Command;
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UINT8 Features;
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UINT8 Fis[5 * 4];
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} SATA_SI3132_FIS;
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typedef struct _SATA_SI3132_PRB {
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UINT16 Control;
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UINT16 ProtocolOverride;
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UINT32 RecTransCount;
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SATA_SI3132_FIS Fis;
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SATA_SI3132_SGE Sge[2];
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} SATA_SI3132_PRB;
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typedef struct _SATA_SI3132_DEVICE {
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LIST_ENTRY Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
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UINTN Index;
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struct _SATA_SI3132_PORT *Port; //Parent Port
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UINT32 BlockSize;
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} SATA_SI3132_DEVICE;
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typedef struct _SATA_SI3132_PORT {
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UINTN Index;
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UINTN RegBase;
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struct _SATA_SI3132_INSTANCE *Instance;
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//TODO: Support Port multiplier
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LIST_ENTRY Devices;
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SATA_SI3132_PRB* HostPRB;
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EFI_PHYSICAL_ADDRESS PhysAddrHostPRB;
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VOID* PciAllocMappingPRB;
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} SATA_SI3132_PORT;
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typedef struct _SATA_SI3132_INSTANCE {
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UINTN Signature;
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SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT];
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EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol;
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EFI_PCI_IO_PROTOCOL *PciIo;
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} SATA_SI3132_INSTANCE;
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#define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2')
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#define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)
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#define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)
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#define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }
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#define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)
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#define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }
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#define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))
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extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName;
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extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;
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/*
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* Component Name Protocol Functions
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*/
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EFI_STATUS
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EFIAPI
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SataSiI3132ComponentNameGetDriverName (
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IN EFI_COMPONENT_NAME_PROTOCOL *This,
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IN CHAR8 *Language,
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OUT CHAR16 **DriverName
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);
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EFI_STATUS
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EFIAPI
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SataSiI3132ComponentNameGetControllerName (
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IN EFI_COMPONENT_NAME_PROTOCOL *This,
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IN EFI_HANDLE ControllerHandle,
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IN EFI_HANDLE ChildHandle OPTIONAL,
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IN CHAR8 *Language,
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OUT CHAR16 **ControllerName
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);
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EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);
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/*
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* Driver Binding Protocol Functions
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*/
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EFI_STATUS
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EFIAPI
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SataSiI3132DriverBindingSupported (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
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);
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EFI_STATUS
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EFIAPI
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SataSiI3132DriverBindingStart (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath
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);
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EFI_STATUS
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EFIAPI
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SataSiI3132DriverBindingStop (
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IN EFI_DRIVER_BINDING_PROTOCOL *This,
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IN EFI_HANDLE Controller,
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IN UINTN NumberOfChildren,
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IN EFI_HANDLE *ChildHandleBuffer
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);
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EFI_STATUS SiI3132AtaPassThruCommand (
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IN SATA_SI3132_INSTANCE *pSataSiI3132Instance,
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IN SATA_SI3132_PORT *pSataPort,
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IN UINT16 PortMultiplierPort,
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IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
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IN EFI_EVENT Event OPTIONAL
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);
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/**
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* EFI ATA Pass Thru Protocol
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*/
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EFI_STATUS SiI3132AtaPassThru (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN UINT16 Port,
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IN UINT16 PortMultiplierPort,
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IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
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IN EFI_EVENT Event OPTIONAL
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);
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EFI_STATUS SiI3132GetNextPort (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN OUT UINT16 *Port
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);
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EFI_STATUS SiI3132GetNextDevice (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN UINT16 Port,
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IN OUT UINT16 *PortMultiplierPort
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);
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EFI_STATUS SiI3132BuildDevicePath (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN UINT16 Port,
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IN UINT16 PortMultiplierPort,
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IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath
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);
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EFI_STATUS SiI3132GetDevice (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
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OUT UINT16 *Port,
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OUT UINT16 *PortMultiplierPort
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);
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EFI_STATUS SiI3132ResetPort (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN UINT16 Port
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);
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EFI_STATUS SiI3132ResetDevice (
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IN EFI_ATA_PASS_THRU_PROTOCOL *This,
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IN UINT16 Port,
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IN UINT16 PortMultiplierPort
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);
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#endif
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