mirror of https://github.com/acidanthera/audk.git
90 lines
3.6 KiB
C
90 lines
3.6 KiB
C
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/** @file
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Support for the PCI Express 4.0 standard.
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This header file may not define all structures. Please extend as required.
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Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PCIEXPRESS40_H_
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#define _PCIEXPRESS40_H_
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#include <IndustryStandard/PciExpress31.h>
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#pragma pack(1)
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/// The Physical Layer PCI Express Extended Capability definitions.
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///
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/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
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///@{
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026
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#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1
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// Register offsets from Physical Layer PCI-E Ext Cap Header
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET 0x04
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET 0x08
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET 0x0C
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET 0x10
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET 0x14
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET 0x18
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#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
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typedef union {
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struct {
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UINT32 Reserved : 32; // Reserved bit 0:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
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typedef union {
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struct {
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UINT32 Reserved : 32; // Reserved bit 0:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
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typedef union {
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struct {
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UINT32 EqualizationComplete : 1; // bit 0
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UINT32 EqualizationPhase1Success : 1; // bit 1
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UINT32 EqualizationPhase2Success : 1; // bit 2
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UINT32 EqualizationPhase3Success : 1; // bit 3
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UINT32 LinkEqualizationRequest : 1; // bit 4
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UINT32 Reserved : 27; // Reserved bit 5:31
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} Bits;
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UINT32 Uint32;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
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typedef union {
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struct {
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UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
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UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7
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} Bits;
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UINT8 Uint8;
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} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
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typedef struct {
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PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablities;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
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UINT32 LocalDataParityMismatchStatus;
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UINT32 FirstRetimerDataParityMismatchStatus;
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UINT32 SecondRetimerDataParityMismatchStatus;
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UINT32 Reserved;
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PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
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} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
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///@}
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#pragma pack()
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#endif
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