2011-02-02 23:35:30 +01:00
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef L2CACHELIB_H_
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#define L2CACHELIB_H_
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#define L2_LATENCY 7
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#define L2_TAG_ACCESS_LATENCY L2_LATENCY
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#define L2_TAG_SETUP_LATENCY L2_LATENCY
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#define L2_DATA_ACCESS_LATENCY L2_LATENCY
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#define L2_DATA_SETUP_LATENCY L2_LATENCY
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#define L2X0_CACHEID 0x000
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#define L2X0_CTRL 0x100
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#define L2X0_AUXCTRL 0x104
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#define L230_TAG_LATENCY 0x108
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#define L230_DATA_LATENCY 0x10C
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#define L2X0_INTCLEAR 0x220
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2011-02-02 23:52:07 +01:00
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#define L2X0_CACHE_SYNC\s\s\s\s\s\s0x730
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2011-02-02 23:35:30 +01:00
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#define L2X0_INVWAY 0x77C
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_PFCTRL 0xF60
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#define L2X0_PWRCTRL 0xF80
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#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
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#define L2X0_CACHEID_PARTNUM_PL310 0x03
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#define L2X0_CTRL_ENABLED 0x1
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#define L2X0_CTRL_DISABLED 0x0
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#define L2X0_AUXCTRL_EXCLUSIVE (1<<12)
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#define L2X0_AUXCTRL_WAYSIZE_16KB (0x001 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_32KB (0x010 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_64KB (0x011 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_128KB (0x100 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_256KB (0x101 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_512KB (0x110 << 17)
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#define L2X0_AUXCTRL_EM (1 << 20)
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#define L2x0_AUXCTRL_AW_AWCACHE (0x00 << 23)
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#define L2x0_AUXCTRL_AW_NOALLOC (0x01 << 23)
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#define L2x0_AUXCTRL_AW_OVERRIDE (0x10 << 23)
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#define L2X0_AUXCTRL_SBO (1 << 25)
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#define L2X0_AUXCTRL_NSAC (1 << 27)
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#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
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#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
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VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);
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#endif /* L2CACHELIB_H_ */
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