mirror of https://github.com/acidanthera/audk.git
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
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/** @file
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Copyright (c) 2011, ARM Limited. All rights reserved.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmCpuLib.h>
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#include <Library/ArmGicLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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VOID
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ArmCpuSynchronizeSignal (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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if (Event == ARM_CPU_EVENT_BOOT_MEM_INIT) {
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// Do nothing, Cortex A9 secondary cores are waiting for the SCU to be
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// enabled (done by ArmCpuSetup()) as a way to know when the Init Boot
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// Mem as been initialized
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} else {
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// Send SGI to all Secondary core to wake them up from WFI state.
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ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
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}
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}
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VOID
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CArmCpuSynchronizeWait (
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IN ARM_CPU_SYNCHRONIZE_EVENT Event
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)
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{
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// Waiting for the SGI from the primary core
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ArmCallWFI ();
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// Acknowledge the interrupt and send End of Interrupt signal.
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ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
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}
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#if 0
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VOID
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ArmEnableScu (
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VOID
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)
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{
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INTN ScuBase;
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ScuBase = ArmGetScuBaseAddress();
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// Invalidate all: write -1 to SCU Invalidate All register
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MmioWrite32(ScuBase + A9_SCU_INVALL_OFFSET, 0xffffffff);
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// Enable SCU
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MmioWrite32(ScuBase + A9_SCU_CONTROL_OFFSET, 0x1);
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}
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#endif
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VOID
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ArmCpuSetup (
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IN UINTN MpId
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)
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{
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/*AMP mode and SMP mode
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By default, the processor is in AMP mode (bit 5 reset to 0). To prevent coherent data corruption the sequence to turn on MP11 CPUs in SMP mode is:
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1.Write the SCU register to change CPU mode.
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2.Disable interrupts.
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3.Clean and invalidate all the D-cache.
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4.Write SMP/nAMP bit as 1.
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5.Enable interrupts.
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Source: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/BIHHFGEC.html
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*/
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// If MPCore then Enable the SCU
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if (ArmIsMpCore()) {
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//ArmEnableScu ();
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}
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}
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VOID
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ArmCpuSetupSmpNonSecure (
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IN UINTN MpId
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)
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{
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#if 0
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INTN ScuBase;
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ArmSetAuxCrBit (A9_FEATURE_SMP);
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// Make the SCU accessible in Non Secure world
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if (IS_PRIMARY_CORE(MpId)) {
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ScuBase = ArmGetScuBaseAddress();
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// Allow NS access to SCU register
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MmioOr32 (ScuBase + A9_SCU_SACR_OFFSET, 0xf);
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// Allow NS access to Private Peripherals
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MmioOr32 (ScuBase + A9_SCU_SSACR_OFFSET, 0xfff);
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}
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#endif
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}
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