MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
/** @file
|
|
|
|
I/O Library for ARM.
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
|
|
|
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
|
|
|
|
Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
|
|
|
|
|
2019-04-04 01:06:00 +02:00
|
|
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
|
|
|
|
**/
|
|
|
|
|
|
|
|
#include "BaseIoLibIntrinsicInternal.h"
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads an 8-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT8
|
|
|
|
EFIAPI
|
|
|
|
MmioRead8Internal (
|
|
|
|
IN UINTN Address
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes an 8-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 8-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite8Internal (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT8 Value
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 16-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT16
|
|
|
|
EFIAPI
|
|
|
|
MmioRead16Internal (
|
|
|
|
IN UINTN Address
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 16-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 16-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite16Internal (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT16 Value
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 32-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT32
|
|
|
|
EFIAPI
|
|
|
|
MmioRead32Internal (
|
|
|
|
IN UINTN Address
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 32-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 32-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite32Internal (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT32 Value
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 64-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
EFIAPI
|
|
|
|
MmioRead64Internal (
|
|
|
|
IN UINTN Address
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 64-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 64-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite64Internal (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT64 Value
|
|
|
|
);
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads an 8-bit I/O port.
|
|
|
|
|
|
|
|
Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 8-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT8
|
|
|
|
EFIAPI
|
|
|
|
IoRead8 (
|
|
|
|
IN UINTN Port
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes an 8-bit I/O port.
|
|
|
|
|
|
|
|
Writes the 8-bit I/O port specified by Port with the value specified by Value
|
|
|
|
and returns Value. This function must guarantee that all I/O read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 8-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Value The value to write to the I/O port.
|
|
|
|
|
|
|
|
@return The value written the I/O port.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT8
|
|
|
|
EFIAPI
|
|
|
|
IoWrite8 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINT8 Value
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 16-bit I/O port.
|
|
|
|
|
|
|
|
Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 16-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT16
|
|
|
|
EFIAPI
|
|
|
|
IoRead16 (
|
|
|
|
IN UINTN Port
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 16-bit I/O port.
|
|
|
|
|
|
|
|
Writes the 16-bit I/O port specified by Port with the value specified by Value
|
|
|
|
and returns Value. This function must guarantee that all I/O read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 16-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Value The value to write to the I/O port.
|
|
|
|
|
|
|
|
@return The value written the I/O port.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT16
|
|
|
|
EFIAPI
|
|
|
|
IoWrite16 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINT16 Value
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 32-bit I/O port.
|
|
|
|
|
|
|
|
Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 32-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT32
|
|
|
|
EFIAPI
|
|
|
|
IoRead32 (
|
|
|
|
IN UINTN Port
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 32-bit I/O port.
|
|
|
|
|
|
|
|
Writes the 32-bit I/O port specified by Port with the value specified by Value
|
|
|
|
and returns Value. This function must guarantee that all I/O read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 32-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Value The value to write to the I/O port.
|
|
|
|
|
|
|
|
@return The value written the I/O port.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT32
|
|
|
|
EFIAPI
|
|
|
|
IoWrite32 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINT32 Value
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 64-bit I/O port.
|
|
|
|
|
|
|
|
Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 64-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
If Port is not aligned on a 64-bit boundary, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
EFIAPI
|
|
|
|
IoRead64 (
|
|
|
|
IN UINTN Port
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 64-bit I/O port.
|
|
|
|
|
|
|
|
Writes the 64-bit I/O port specified by Port with the value specified by Value
|
|
|
|
and returns Value. This function must guarantee that all I/O read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 64-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
If Port is not aligned on a 64-bit boundary, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Value The value to write to the I/O port.
|
|
|
|
|
|
|
|
@return The value written to the I/O port.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
EFIAPI
|
|
|
|
IoWrite64 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINT64 Value
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads an 8-bit I/O port fifo into a block of memory.
|
|
|
|
|
|
|
|
Reads the 8-bit I/O fifo port specified by Port.
|
|
|
|
The port is read Count times, and the read data is
|
|
|
|
stored in the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 8-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
@param Count The number of times to read I/O port.
|
|
|
|
@param Buffer The buffer to store the read data into.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoReadFifo8 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
OUT VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a block of memory into an 8-bit I/O port fifo.
|
|
|
|
|
|
|
|
Writes the 8-bit I/O fifo port specified by Port.
|
|
|
|
The port is written Count times, and the write data is
|
|
|
|
retrieved from the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O write and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 8-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Count The number of times to write I/O port.
|
|
|
|
@param Buffer The buffer to retrieve the write data from.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoWriteFifo8 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
IN VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 16-bit I/O port fifo into a block of memory.
|
|
|
|
|
|
|
|
Reads the 16-bit I/O fifo port specified by Port.
|
|
|
|
The port is read Count times, and the read data is
|
|
|
|
stored in the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 16-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
@param Count The number of times to read I/O port.
|
|
|
|
@param Buffer The buffer to store the read data into.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoReadFifo16 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
OUT VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a block of memory into a 16-bit I/O port fifo.
|
|
|
|
|
|
|
|
Writes the 16-bit I/O fifo port specified by Port.
|
|
|
|
The port is written Count times, and the write data is
|
|
|
|
retrieved from the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O write and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 16-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Count The number of times to write I/O port.
|
|
|
|
@param Buffer The buffer to retrieve the write data from.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoWriteFifo16 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
IN VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 32-bit I/O port fifo into a block of memory.
|
|
|
|
|
|
|
|
Reads the 32-bit I/O fifo port specified by Port.
|
|
|
|
The port is read Count times, and the read data is
|
|
|
|
stored in the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O read and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 32-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to read.
|
|
|
|
@param Count The number of times to read I/O port.
|
|
|
|
@param Buffer The buffer to store the read data into.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoReadFifo32 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
OUT VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a block of memory into a 32-bit I/O port fifo.
|
|
|
|
|
|
|
|
Writes the 32-bit I/O fifo port specified by Port.
|
|
|
|
The port is written Count times, and the write data is
|
|
|
|
retrieved from the provided Buffer.
|
|
|
|
|
|
|
|
This function must guarantee that all I/O write and write operations are
|
|
|
|
serialized.
|
|
|
|
|
|
|
|
If 32-bit I/O port operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Port The I/O port to write.
|
|
|
|
@param Count The number of times to write I/O port.
|
|
|
|
@param Buffer The buffer to retrieve the write data from.
|
|
|
|
|
|
|
|
**/
|
|
|
|
VOID
|
|
|
|
EFIAPI
|
|
|
|
IoWriteFifo32 (
|
|
|
|
IN UINTN Port,
|
|
|
|
IN UINTN Count,
|
|
|
|
IN VOID *Buffer
|
|
|
|
)
|
|
|
|
{
|
|
|
|
ASSERT (FALSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads an 8-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 8-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT8
|
|
|
|
EFIAPI
|
|
|
|
MmioRead8 (
|
|
|
|
IN UINTN Address
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
UINT8 Value;
|
|
|
|
BOOLEAN Flag;
|
|
|
|
|
|
|
|
Flag = FilterBeforeMmIoRead (FilterWidth8, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
Value = MmioRead8Internal (Address);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoRead (FilterWidth8, Address, &Value);
|
|
|
|
|
|
|
|
return Value;
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes an 8-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 8-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
If 8-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT8
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite8 (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT8 Value
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
|
|
|
|
Flag = FilterBeforeMmIoWrite (FilterWidth8, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
MmioWrite8Internal (Address, Value);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoWrite (FilterWidth8, Address, &Value);
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 16-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 16-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT16
|
|
|
|
EFIAPI
|
|
|
|
MmioRead16 (
|
|
|
|
IN UINTN Address
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
UINT16 Value;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 1) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoRead (FilterWidth16, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
Value = MmioRead16Internal (Address);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoRead (FilterWidth16, Address, &Value);
|
|
|
|
|
|
|
|
return Value;
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 16-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 16-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
If 16-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT16
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite16 (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT16 Value
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 1) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoWrite (FilterWidth16, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
MmioWrite16Internal (Address, Value);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoWrite (FilterWidth16, Address, &Value);
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 32-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 32-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT32
|
|
|
|
EFIAPI
|
|
|
|
MmioRead32 (
|
|
|
|
IN UINTN Address
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
UINT32 Value;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 3) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoRead (FilterWidth32, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
Value = MmioRead32Internal (Address);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoRead (FilterWidth32, Address, &Value);
|
|
|
|
|
|
|
|
return Value;
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 32-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 32-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
If 32-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT32
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite32 (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT32 Value
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 3) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoWrite (FilterWidth32, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
MmioWrite32Internal (Address, Value);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoWrite (FilterWidth32, Address, &Value);
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
return Value;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Reads a 64-bit MMIO register.
|
|
|
|
|
|
|
|
Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
|
|
|
|
returned. This function must guarantee that all MMIO read and write
|
|
|
|
operations are serialized.
|
|
|
|
|
|
|
|
If 64-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to read.
|
|
|
|
|
|
|
|
@return The value read.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
EFIAPI
|
|
|
|
MmioRead64 (
|
|
|
|
IN UINTN Address
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
UINT64 Value;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 7) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoRead (FilterWidth64, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
Value = MmioRead64Internal (Address);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoRead (FilterWidth64, Address, &Value);
|
|
|
|
|
|
|
|
return Value;
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Writes a 64-bit MMIO register.
|
|
|
|
|
|
|
|
Writes the 64-bit MMIO register specified by Address with the value specified
|
|
|
|
by Value and returns Value. This function must guarantee that all MMIO read
|
|
|
|
and write operations are serialized.
|
|
|
|
|
|
|
|
If 64-bit MMIO register operations are not supported, then ASSERT().
|
|
|
|
|
|
|
|
@param Address The MMIO register to write.
|
|
|
|
@param Value The value to write to the MMIO register.
|
|
|
|
|
|
|
|
**/
|
|
|
|
UINT64
|
|
|
|
EFIAPI
|
|
|
|
MmioWrite64 (
|
|
|
|
IN UINTN Address,
|
|
|
|
IN UINT64 Value
|
|
|
|
)
|
|
|
|
{
|
2021-03-12 03:26:10 +01:00
|
|
|
BOOLEAN Flag;
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
|
|
|
ASSERT ((Address & 7) == 0);
|
|
|
|
|
2021-03-12 03:26:10 +01:00
|
|
|
Flag = FilterBeforeMmIoWrite (FilterWidth64, Address, &Value);
|
|
|
|
if (Flag) {
|
|
|
|
MmioWrite64Internal (Address, Value);
|
|
|
|
}
|
|
|
|
FilterAfterMmIoWrite (FilterWidth64, Address, &Value);
|
|
|
|
|
MdePkg/BaseIoLibIntrinsic: make BaseIoLibIntrinsic safe for ArmVirt/KVM
KVM on ARM refuses to decode load/store instructions used to perform
I/O to emulated devices, and instead relies on the exception syndrome
information to describe the operand register, access size, etc.
This is only possible for instructions that have a single input/output
register (as opposed to ones that increment the offset register, or
load/store pair instructions, etc). Otherwise, QEMU crashes with the
following error
error: kvm run failed Function not implemented
R00=01010101 R01=00000008 R02=00000048 R03=08000820
R04=00000120 R05=7faaa0e0 R06=7faaa0dc R07=7faaa0e8
R08=7faaa0ec R09=7faaa088 R10=000000ff R11=00000080
R12=ff000000 R13=7fccfe08 R14=7faa835f R15=7faa887c
PSR=800001f3 N--- T svc32
QEMU: Terminated
and KVM produces a warning such as the following in the kernel log
kvm [17646]: load/store instruction decoding not implemented
The IoLib implementation provided by MdePkg/Library/BaseIoLibIntrinsic
is based on C code, and when LTO is in effect, the MMIO accesses could
be merged with, e.g., manipulations of the loop counter, producing
opcodes that KVM does not support for emulated MMIO.
So let's add a special ArmVirt flavor of this library that implements
that actual load/store operations in assembler, ensuring that the
instructions involved can be emulated by KVM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2018-06-07 12:44:12 +02:00
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return Value;
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}
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