2011-02-02 23:35:30 +01:00
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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2011-07-06 18:35:30 +02:00
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#include <Uefi.h>
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2011-02-02 23:35:30 +01:00
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#include <Library/IoLib.h>
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#include <Drivers/PL390Gic.h>
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VOID
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EFIAPI
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PL390GicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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2011-02-03 00:19:30 +01:00
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{
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/*
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2011-07-06 18:35:30 +02:00
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* Enable the CPU interface in Non-Secure world
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* Note: The ICCICR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
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2011-02-02 23:35:30 +01:00
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}
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VOID
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EFIAPI
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PL390GicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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2011-07-06 18:35:30 +02:00
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/*
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* Enable GIC distributor in Non-Secure world.
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* Note: The ICDDCR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
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2011-02-02 23:35:30 +01:00
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}
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VOID
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EFIAPI
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PL390GicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList
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)
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{
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2011-07-06 18:35:30 +02:00
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MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
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2011-02-02 23:35:30 +01:00
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgiFrom (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId
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)
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{
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2011-07-06 18:35:30 +02:00
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INTN InterruptId;
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2011-02-02 23:35:30 +01:00
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2011-07-06 18:35:30 +02:00
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
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2011-02-02 23:35:30 +01:00
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2011-07-06 18:35:30 +02:00
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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2011-02-03 00:19:30 +01:00
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if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
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2011-07-06 18:35:30 +02:00
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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2011-02-02 23:35:30 +01:00
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgi2From (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId,
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IN INTN SgiId
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)
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{
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2011-07-06 18:35:30 +02:00
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INTN InterruptId;
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2011-02-02 23:35:30 +01:00
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2011-07-06 18:35:30 +02:00
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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2011-02-02 23:35:30 +01:00
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2011-07-06 18:35:30 +02:00
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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2011-02-03 00:19:30 +01:00
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if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
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2011-07-06 18:35:30 +02:00
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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2011-02-02 23:35:30 +01:00
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}
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