2015-05-13 11:31:10 +02:00
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/** @file
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Various register numbers and value bits based on the following publications:
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- Intel(R) datasheet 290549-001
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- Intel(R) datasheet 290562-001
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- Intel(R) datasheet 297654-006
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- Intel(R) datasheet 297738-017
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (c) 2014, Gabriel L. Somlo <somlo@cmu.edu>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __I440FX_PIIX4_H__
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#define __I440FX_PIIX4_H__
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#include <Library/PciLib.h>
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//
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// Host Bridge Device ID (DID) value for I440FX
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//
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#define INTEL_82441_DEVICE_ID 0x1237
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OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
* Introduce the PIIX4_PAM* and MCH_PAM* macros under
"OvmfPkg/Include/IndustryStandard". These macros capture the PAM
register offsets (in PCI config space) on the respective Memory
Controller B/D/F, from the respective data sheets.
* Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for
PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases,
the B/D/F is 0/0/0.
* Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the
PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new
field contains the return value of the PCI_LIB_ADDRESS() macro.
* Under CsmSupportLib, replace the "mRegisterValues440" elements as
follows:
REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData
-->
PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData
* Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as
follows:
REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData
-->
DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData
* Under CsmSupportLib, update the register address calculations as follows
(for all of PciOr8(), PciAnd8() and PciRead8()):
PCI_LIB_ADDRESS (
PAM_PCI_BUS,
PAM_PCI_DEV,
PAM_PCI_FUNC,
mRegisterValues[Index].PAMRegOffset
)
-->
mRegisterValues[Index].PAMRegPciLibAddress
* Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros.
Technically speaking, these changes could be split into three patches
(IndustryStandard macro additions, CsmSupportLib code updates,
CsmSupportLib macro removals). However, the patch is not big, and in this
case it is actually helpful to present the code movement / refactoring in
one step, for easier verification.
Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Aleksei Kovura <alex3kov@zoho.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-09-19 15:50:39 +02:00
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//
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// B/D/F/Type: 0/0/0/PCI
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//
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#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
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#define PIIX4_PAM0 0x59
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#define PIIX4_PAM1 0x5A
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#define PIIX4_PAM2 0x5B
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#define PIIX4_PAM3 0x5C
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#define PIIX4_PAM4 0x5D
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#define PIIX4_PAM5 0x5E
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#define PIIX4_PAM6 0x5F
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2015-05-13 11:31:10 +02:00
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//
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// B/D/F/Type: 0/1/3/PCI
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//
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#define POWER_MGMT_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 1, 3, (Offset))
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2015-05-13 11:31:39 +02:00
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#define PIIX4_PMBA 0x40
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2016-05-09 20:05:18 +02:00
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#define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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BIT10 | BIT9 | BIT8 | BIT7 | BIT6)
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2015-05-13 11:31:39 +02:00
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#define PIIX4_PMREGMISC 0x80
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#define PIIX4_PMREGMISC_PMIOSE BIT0
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2015-05-13 11:31:10 +02:00
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#endif
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