2015-01-12 10:37:20 +01:00
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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2019-04-04 01:07:37 +02:00
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SPDX-License-Identifier: BSD-2-Clause-Patent
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2015-01-12 10:37:20 +01:00
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Module Name:
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ClockControl.c
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Abstract:
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Sets platform/SKU specific clock routing information.
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--*/
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#include "PlatformDxe.h"
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#include <Protocol/CK505ClockPlatformInfo.h>
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//
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// Default clock routing informtion (All On)
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//
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EFI_CLOCK_PLATFORM_INFO mDefClockPolicy = {NULL, 0, NULL, 0, NULL, 0};
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//
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// Clock Settings
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//
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// Static clock table.
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// This should be used to define any clock settings that are static
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// (Always On or Always Off). Dynamic clocks should be set to enabled
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// in this table.
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//
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EFI_STATIC_SIGNALS mAtxStaticClocks[] = {
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{SrcClk8, Enabled, All},
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{SrcClk7, Enabled, All},
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{SrcClk6, Enabled, All},
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{SrcClk5, Enabled, All},
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{SrcClk4, Enabled, All},
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{SrcClk3, Enabled, All},
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{SrcClk2, Enabled, All},
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{SrcClk1, Enabled, All},
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{SrcClk0, Enabled, All},
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{Ref0, Enabled, All},
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{Dot96, Enabled, All},
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{Usb48, Enabled, All},
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{PciClkF5, Enabled, All},
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{PciClk0, Enabled, All},
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{PciClk2, Enabled, All},
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{PciClk3, Enabled, All},
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{PciClk4, Disabled, All},
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{Cr_B, EnabledWithSwitch, All},
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};
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//
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// ClockSxInfo Table
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// This is a list of clocks that need to be set to a known state when the
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// system enters S4 or S5.
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//
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EFI_STATIC_SIGNALS mAtxSxClocks[] = {
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{SaveClockConfiguration, Disabled, All}
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};
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//
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// ATX settings structure
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//
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EFI_CLOCK_PLATFORM_INFO mAtxClockSettings = {
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mAtxStaticClocks,
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sizeof(mAtxStaticClocks) / sizeof(mAtxStaticClocks[0]),
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mAtxSxClocks,
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sizeof(mAtxSxClocks) / sizeof(mAtxSxClocks[0])
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};
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#if defined( RVP_SUPPORT ) && RVP_SUPPORT
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//
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// RVP Clock Settings
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//
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// Static clock table.
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// This should be used to define any clock settings that are static
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// (Always On or Always Off). Dynamic clocks should be set to enabled
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// in this table.
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//
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//UPSD_TBD Check with Jan if any porting required.
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//
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EFI_STATIC_SIGNALS mRvpStaticClocks[] = {
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{SrcClk11, Enabled, All}, // Not used/not present but leave coding enabled
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{SrcClk10, Enabled, All}, // Not used/not present but leave coding enabled
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{SrcClk9, Enabled, All}, // Not used/not present but leave coding enabled
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{SrcClk8, Enabled, All}, // ICHSATAII
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{SrcClk7, Enabled, All}, // DPL_REFSSCLKIN
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{SrcClk6, Enabled, All}, // 100M_MCH
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{SrcClk5, Enabled, All}, // Mini-PCIe //TODO PNV: Need to check ICH GPIO38:
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// 0: turn on; 1: turn off
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{SrcClk4, Enabled, All}, // ICHSATA
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{SrcClk3, Enabled, All}, // 100M_ICH
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{SrcClk2, Enabled, All}, // 100M_LAN
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{SrcClk1, Enabled, All}, // 25M_LAN
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{SrcClk0, Enabled, All}, // 96M_DREF
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{Ref0, Enabled, All},
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{Dot96, Enabled, All},
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{Usb48, Enabled, All},
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{PciClkF5, Enabled, All}, // 33M_ICH
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{PciClk0, Enabled, All}, // 33M_RISER
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{PciClk1, Enabled, All}, // 33M_RISER
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{PciClk2, Enabled, All}, // VDD_Clock
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{PciClk3, Enabled, All}, // 33M_S1
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{PciClk4, Enabled, All}, // 33M_PA
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};
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//
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// Dynamic clock table
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// This is used to determine if a clock should be left on or turned off based
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// on the presence of a device. The bridge information is used so the bus
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// number for the device to be detected can be found.
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//
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//
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// ClockSxInfo Table
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// This is a list of clocks that need to be set to a known state when the
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// system enters S4 or S5.
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//
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EFI_STATIC_SIGNALS mRvpSxClocks[] = {
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{SaveClockConfiguration, Disabled, All}
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};
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//
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// RVP settings structure
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//
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EFI_CLOCK_PLATFORM_INFO mRvpClockSettings = {
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mRvpStaticClocks,
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sizeof(mRvpStaticClocks) / sizeof(mRvpStaticClocks[0]),
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0, // No clocks will be turned off mRvpDynamicClocks,
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0, // No clocks will be turned off sizeof(mRvpDynamicClocks) / sizeof(mRvpDynamicClocks[0]),
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mRvpSxClocks,
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sizeof(mRvpSxClocks) / sizeof(mRvpSxClocks[0])
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};
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#endif
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VOID
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InitializeClockRouting(
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)
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{
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EFI_STATUS Status;
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UINTN BoardIdVarSize;
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EFI_BOARD_FEATURES BoardIdVar;
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EFI_CLOCK_PLATFORM_INFO *ClockPolicy;
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EFI_HANDLE Handle;
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ClockPolicy = &mDefClockPolicy;
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//
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// Do modifications based on board type
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//
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BoardIdVarSize = sizeof (EFI_BOARD_FEATURES);
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Status = gRT->GetVariable (
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BOARD_FEATURES_NAME,
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&gEfiBoardFeaturesGuid,
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NULL,
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&BoardIdVarSize,
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&BoardIdVar
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);
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if (!EFI_ERROR (Status)) {
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#if defined( RVP_SUPPORT ) && RVP_SUPPORT
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if (BoardIdVar & B_BOARD_FEATURES_RVP) {
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ClockPolicy = &mRvpClockSettings;
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}
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#else
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//
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// Isolate board type information
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//
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BoardIdVar = BoardIdVar & (B_BOARD_FEATURES_FORM_FACTOR_ATX |
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B_BOARD_FEATURES_FORM_FACTOR_BTX |
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B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX |
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B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX);
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if (BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_ATX ||
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BoardIdVar == B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX) {
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ClockPolicy = &mAtxClockSettings;
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}
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#endif
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}
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Handle = NULL;
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Status = gBS->InstallProtocolInterface (
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&Handle,
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&gEfiCk505ClockPlatformInfoGuid,
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EFI_NATIVE_INTERFACE,
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ClockPolicy
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);
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ASSERT_EFI_ERROR(Status);
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}
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