mirror of https://github.com/acidanthera/audk.git
113 lines
3.3 KiB
ArmAsm
113 lines
3.3 KiB
ArmAsm
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#------------------------------------------------------------------------------
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#
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# ARM VE Entry point. Reset vector in FV header will brach to
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# _ModuleEntryPoint.
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <AutoGen.h>
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#Start of Code section
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.text
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.align 3
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#make _ModuleEntryPoint as global
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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#global functions referenced by this module
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GCC_ASM_IMPORT(CEntryPoint)
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GCC_ASM_IMPORT(ArmPlatformIsMemoryInitialized)
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GCC_ASM_IMPORT(ArmPlatformInitializeBootMemory)
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GCC_ASM_IMPORT(ArmDisableInterrupts)
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GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
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GCC_ASM_IMPORT(ArmWriteVBar)
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GCC_ASM_IMPORT(SecVectorTable)
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#if (FixedPcdGet32(PcdMPCoreSupport))
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GCC_ASM_IMPORT(ArmIsScuEnable)
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#endif
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StartupAddr: .word CEntryPoint
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SecVectorTableAddr: .word SecVectorTable
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ASM_PFX(_ModuleEntryPoint):
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#Set VBAR to the start of the exception vectors in Secure Mode
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ldr r0, SecVectorTableAddr
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bl ASM_PFX(ArmWriteVBar)
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# First ensure all interrupts are disabled
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bl ASM_PFX(ArmDisableInterrupts)
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# Ensure that the MMU and caches are off
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bl ASM_PFX(ArmDisableCachesAndMmu)
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_IdentifyCpu:
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# Identify CPU ID
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bl ASM_PFX(ArmReadMpidr)
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and r5, r0, #0xf
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#get ID of this CPU in Multicore system
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cmp r5, #0
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# Only the primary core initialize the memory (SMC)
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beq _InitMem
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#if (FixedPcdGet32(PcdMPCoreSupport))
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# ... The secondary cores wait for SCU to be enabled
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_WaitForEnabledScu:
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bl ASM_PFX(ArmIsScuEnable)
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tst r1, #1
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beq _WaitForEnabledScu
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b _SetupStack
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#endif
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_InitMem:
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bl ASM_PFX(ArmPlatformIsMemoryInitialized)
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bne _SetupStack
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# Initialize Init Memory
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bl ASM_PFX(ArmPlatformInitializeBootMemory)
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# Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
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mov r5, #0
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_SetupStack:
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# Setup Stack for the 4 CPU cores
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#Read Stack Base address from PCD
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase) ,r1)
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#read Stack size from PCD
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecStackSize) ,r2)
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#calcuate Stack Pointer reg value using Stack size and CPU ID.
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mov r3,r5 @ r3 = core_id
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mul r3,r3,r2 @ r3 = core_id * stack_size = offset from the stack base
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add r3,r3,r1 @ r3 ldr= stack_base + offset
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mov sp, r3
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# move sec startup address into a data register
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# ensure we're jumping to FV version of the code (not boot remapped alias)
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ldr r3, StartupAddr
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# Move the CoreId in r0 to be the first argument of the SEC Entry Point
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mov r0, r5
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# jump to SEC C code
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# r0 = core_id
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blx r3
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.end
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