mirror of https://github.com/acidanthera/audk.git
76 lines
2.0 KiB
C
76 lines
2.0 KiB
C
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/** @file
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ArmGicArchLib library class implementation for DT based virt platforms
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Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/ArmGicLib.h>
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#include <Library/ArmGicArchLib.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
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RETURN_STATUS
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EFIAPI
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ArmVirtGicArchLibConstructor (
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VOID
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)
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{
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UINT32 IccSre;
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switch (PcdGet32 (PcdArmGicRevision)) {
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case 3:
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//
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// The default implementation of ArmGicArchLib is responsible for enabling
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// the system register interface on the GICv3 if one is found. So let's do
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// the same here.
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//
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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if (!(IccSre & ICC_SRE_EL2_SRE)) {
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ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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}
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//
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// Unlike the default implementation, there is no fall through to GICv2
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// mode if this GICv3 cannot be driven in native mode due to the fact
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// that the System Register interface is unavailable.
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//
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ASSERT (IccSre & ICC_SRE_EL2_SRE);
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mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
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break;
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case 2:
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mGicArchRevision = ARM_GIC_ARCH_REVISION_2;
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break;
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default:
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DEBUG ((EFI_D_ERROR, "%a: No GIC revision specified!\n", __FUNCTION__));
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return RETURN_NOT_FOUND;
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}
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return RETURN_SUCCESS;
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}
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ARM_GIC_ARCH_REVISION
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EFIAPI
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ArmGicGetSupportedArchRevision (
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VOID
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)
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{
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return mGicArchRevision;
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}
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