mirror of https://github.com/acidanthera/audk.git
184 lines
8.2 KiB
C
184 lines
8.2 KiB
C
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/** @file
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Macros to simplify and abstract the interface to PCI configuration.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _QNC_ACCESS_H_
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#define _QNC_ACCESS_H_
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#include "QuarkNcSocId.h"
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#include "QNCCommonDefinitions.h"
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#define EFI_LPC_PCI_ADDRESS( Register ) \
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EFI_PCI_ADDRESS(PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, Register)
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//
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// QNC Controller PCI access macros
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//
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#define QNC_RCRB_BASE (QNCMmio32 (PciDeviceMmBase (0, PCI_DEVICE_NUMBER_QNC_LPC, 0), R_QNC_LPC_RCBA) & B_QNC_LPC_RCBA_MASK)
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//
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// Device 0x1f, Function 0
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//
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#define LpcPciCfg32( Register ) \
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QNCMmPci32(0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
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#define LpcPciCfg32Or( Register, OrData ) \
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QNCMmPci32Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
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#define LpcPciCfg32And( Register, AndData ) \
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QNCMmPci32And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
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#define LpcPciCfg32AndThenOr( Register, AndData, OrData ) \
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QNCMmPci32AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
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#define LpcPciCfg16( Register ) \
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QNCMmPci16( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
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#define LpcPciCfg16Or( Register, OrData ) \
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QNCMmPci16Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
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#define LpcPciCfg16And( Register, AndData ) \
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QNCMmPci16And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
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#define LpcPciCfg16AndThenOr( Register, AndData, OrData ) \
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QNCMmPci16AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
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#define LpcPciCfg8( Register ) \
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QNCMmPci8( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register )
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#define LpcPciCfg8Or( Register, OrData ) \
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QNCMmPci8Or( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, OrData )
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#define LpcPciCfg8And( Register, AndData ) \
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QNCMmPci8And( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData )
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#define LpcPciCfg8AndThenOr( Register, AndData, OrData ) \
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QNCMmPci8AndThenOr( 0,PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, 0, Register, AndData, OrData )
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//
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// Root Complex Register Block
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//
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#define MmRcrb32( Register ) \
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QNCMmio32( QNC_RCRB_BASE, Register )
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#define MmRcrb32Or( Register, OrData ) \
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QNCMmio32Or( QNC_RCRB_BASE, Register, OrData )
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#define MmRcrb32And( Register, AndData ) \
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QNCMmio32And( QNC_RCRB_BASE, Register, AndData )
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#define MmRcrb32AndThenOr( Register, AndData, OrData ) \
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QNCMmio32AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
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#define MmRcrb16( Register ) \
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QNCMmio16( QNC_RCRB_BASE, Register )
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#define MmRcrb16Or( Register, OrData ) \
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QNCMmio16Or( QNC_RCRB_BASE, Register, OrData )
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#define MmRcrb16And( Register, AndData ) \
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QNCMmio16And( QNC_RCRB_BASE, Register, AndData )
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#define MmRcrb16AndThenOr( Register, AndData, OrData ) \
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QNCMmio16AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
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#define MmRcrb8( Register ) \
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QNCMmio8( QNC_RCRB_BASE, Register )
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#define MmRcrb8Or( Register, OrData ) \
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QNCMmio8Or( QNC_RCRB_BASE, Register, OrData )
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#define MmRcrb8And( Register, AndData ) \
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QNCMmio8And( QNC_RCRB_BASE, Register, AndData )
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#define MmRcrb8AndThenOr( Register, AndData, OrData ) \
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QNCMmio8AndThenOr( QNC_RCRB_BASE, Register, AndData, OrData )
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//
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// Memory Controller PCI access macros
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//
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//
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// Device 0, Function 0
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//
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#define McD0PciCfg64(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg64Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg64And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg64AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg32(Register) QNCMmPci32 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg32Or(Register, OrData) QNCMmPci32Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg32And(Register, AndData) QNCMmPci32And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg32AndThenOr(Register, AndData, OrData) QNCMmPci32AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg16(Register) QNCMmPci16 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg16Or(Register, OrData) QNCMmPci16Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg16And(Register, AndData) QNCMmPci16And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg16AndThenOr(Register, AndData, OrData) QNCMmPci16AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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#define McD0PciCfg8(Register) QNCMmPci8 (0, MC_BUS, 0, 0, Register)
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#define McD0PciCfg8Or(Register, OrData) QNCMmPci8Or (0, MC_BUS, 0, 0, Register, OrData)
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#define McD0PciCfg8And(Register, AndData) QNCMmPci8And (0, MC_BUS, 0, 0, Register, AndData)
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#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) QNCMmPci8AndThenOr (0, MC_BUS, 0, 0, Register, AndData, OrData)
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//
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// Memory Controller Hub Memory Mapped IO register access ???
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//
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#define MCH_REGION_BASE (McD0PciCfg64 (MC_MCHBAR_OFFSET) & ~BIT0)
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#define McMmioAddress(Register) ((UINTN) MCH_REGION_BASE + (UINTN) (Register))
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#define McMmio32Ptr(Register) ((volatile UINT32*) McMmioAddress (Register))
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#define McMmio64Ptr(Register) ((volatile UINT64*) McMmioAddress (Register))
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#define McMmio64(Register) *McMmio64Ptr( Register )
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#define McMmio64Or(Register, OrData) (McMmio64 (Register) |= (UINT64)(OrData))
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#define McMmio64And(Register, AndData) (McMmio64 (Register) &= (UINT64)(AndData))
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#define McMmio64AndThenOr(Register, AndData, OrData) (McMmio64 ( Register ) = (McMmio64( Register ) & (UINT64)(AndData)) | (UINT64)(OrData))
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#define McMmio32(Register) *McMmio32Ptr (Register)
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#define McMmio32Or(Register, OrData) (McMmio32 (Register) |= (UINT32)(OrData))
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#define McMmio32And(Register, AndData) (McMmio32 (Register) &= (UINT32)(AndData))
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#define McMmio32AndThenOr(Register, AndData, OrData) (McMmio32 (Register) = (McMmio32 (Register) & (UINT32) (AndData)) | (UINT32) (OrData))
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#define McMmio16Ptr(Register) ((volatile UINT16*) McMmioAddress (Register))
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#define McMmio16(Register) *McMmio16Ptr (Register)
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#define McMmio16Or(Register, OrData) (McMmio16 (Register) |= (UINT16) (OrData))
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#define McMmio16And(Register, AndData) (McMmio16 (Register) &= (UINT16) (AndData))
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#define McMmio16AndThenOr(Register, AndData, OrData) (McMmio16 (Register) = (McMmio16 (Register) & (UINT16) (AndData)) | (UINT16) (OrData))
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#define McMmio8Ptr(Register) ((volatile UINT8 *)McMmioAddress (Register))
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#define McMmio8(Register) *McMmio8Ptr (Register)
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#define McMmio8Or(Register, OrData) (McMmio8 (Register) |= (UINT8) (OrData))
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#define McMmio8And(Register, AndData) (McMmio8 (Register) &= (UINT8) (AndData))
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#define McMmio8AndThenOr(Register, AndData, OrData) (McMmio8 (Register) = (McMmio8 (Register) & (UINT8) (AndData)) | (UINT8) (OrData))
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//
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// QNC memory mapped related data structure deifinition
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//
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typedef enum {
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QNCMmioWidthUint8 = 0,
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QNCMmioWidthUint16 = 1,
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QNCMmioWidthUint32 = 2,
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QNCMmioWidthUint64 = 3,
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QNCMmioWidthMaximum
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} QNC_MEM_IO_WIDTH;
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#endif
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