2016-01-18 05:50:18 +01:00
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/** @file
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The Header file of the Pci Host Bridge Driver.
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Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
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2019-04-04 01:05:13 +02:00
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SPDX-License-Identifier: BSD-2-Clause-Patent
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2016-01-18 05:50:18 +01:00
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**/
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#ifndef _PCI_HOST_RESOURCE_H_
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#define _PCI_HOST_RESOURCE_H_
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#include <PiDxe.h>
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2016-07-14 11:53:50 +02:00
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#define PCI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
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2016-01-18 05:50:18 +01:00
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typedef enum {
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TypeIo = 0,
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TypeMem32,
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TypePMem32,
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TypeMem64,
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TypePMem64,
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TypeBus,
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TypeMax
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} PCI_RESOURCE_TYPE;
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typedef enum {
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ResNone,
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ResSubmitted,
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ResAllocated,
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ResStatusMax
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} RES_STATUS;
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typedef struct {
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PCI_RESOURCE_TYPE Type;
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MdeModulePkg/PciHostBridgeDxe: Add support for address translation
PCI address translation is necessary for some non-x86 platforms. On
such platforms, address value (denoted as "device address" or "address
in PCI view") set to PCI BAR registers in configuration space might be
different from the address which is used by CPU to access the
registers in memory BAR or IO BAR spaces (denoted as "host address" or
"address in CPU view"). The difference between the two addresses is
called "Address Translation Offset" or simply "translation", and can
be represented by "Address Translation Offset" in ACPI QWORD Address
Space Descriptor (Offset 0x1E). However UEFI and ACPI differs on the
definitions of QWORD Address Space Descriptor, and we will follow UEFI
definition on UEFI protocols, such as PCI root bridge IO protocol and
PCI IO protocol. In UEFI 2.7, "Address Translation Offset" is "Offset
to apply to the Starting address to convert it to a PCI address". This
means:
1. Translation = device address - host address.
2. PciRootBridgeIo->Configuration should return CPU view address, as
well as PciIo->GetBarAttributes.
Summary of addresses used in protocol interfaces and internal
implementations:
1. *Only* the following protocol interfaces assume Address is Device
Address:
(1). PciHostBridgeResourceAllocation.GetProposedResources()
Otherwise PCI bus driver cannot set correct address into PCI
BARs.
(2). PciRootBridgeIo.Mem.Read() and PciRootBridgeIo.Mem.Write()
(3). PciRootBridgeIo.CopyMem()
UEFI and PI spec have clear statements for all other protocol
interfaces about the address type.
2. Library interfaces and internal implementation:
(1). Base and Limit in PCI_ROOT_BRIDGE_APERTURE are device address.
It is easy to check whether the address is below 4G or above 4G.
(2). Addresses in PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode are host
address, for they are allocated from GCD.
(3). Address passed to PciHostBridgeResourceConflict is host address,
for it comes from PCI_ROOT_BRIDGE_INSTANCE.ResAllocNode.
RESTRICTION: to simplify the situation, we require the alignment of
Translation must be larger than any BAR alignment in the same root
bridge, so that resource allocation alignment can be applied to both
device address and host address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-08 04:13:26 +01:00
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//
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// Base is a host address
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//
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2016-01-18 05:50:18 +01:00
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UINT64 Base;
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UINT64 Length;
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UINT64 Alignment;
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RES_STATUS Status;
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} PCI_RES_NODE;
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#endif
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