2007-06-22 05:21:45 +02:00
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/** @file
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AsmFlushCacheLine function
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2010-04-23 18:00:47 +02:00
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Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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2007-06-22 05:21:45 +02:00
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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2010-06-11 02:02:51 +02:00
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http://opensource.org/licenses/bsd-license.php.
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2007-06-22 05:21:45 +02:00
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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2008-09-17 09:46:17 +02:00
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2007-06-30 01:22:13 +02:00
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2007-06-22 05:21:45 +02:00
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2008-07-25 14:21:57 +02:00
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/**
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Flushes a cache line from all the instruction and data caches within the
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coherency domain of the CPU.
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Flushed the cache line specified by LinearAddress, and returns LinearAddress.
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2008-12-05 04:23:13 +01:00
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This function is only available on IA-32 and x64.
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2008-07-25 14:21:57 +02:00
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@param LinearAddress The address of the cache line to flush. If the CPU is
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in a physical addressing mode, then LinearAddress is a
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physical address. If the CPU is in a virtual
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addressing mode, then LinearAddress is a virtual
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address.
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@return LinearAddress
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**/
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2007-06-22 05:21:45 +02:00
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VOID *
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EFIAPI
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AsmFlushCacheLine (
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IN VOID *LinearAddress
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)
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{
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_asm {
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mov eax, LinearAddress
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clflush [eax]
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}
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}
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