mirror of https://github.com/acidanthera/audk.git
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
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/** @file
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*
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* Copyright (c) 2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials are licensed and made available
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* under the terms and conditions of the BSD License which accompanies this
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* distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/ArmLib.h>
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#include <Library/ArmGicLib.h>
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ARM_GIC_ARCH_REVISION
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EFIAPI
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ArmGicGetSupportedArchRevision (
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VOID
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)
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{
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UINT32 IccSre;
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// Ideally we would like to use the GICC IIDR Architecture version here, but
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// this does not seem to be very reliable as the implementation could easily
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// get it wrong. It is more reliable to check if the GICv3 System Register
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// feature is implemented on the CPU. This is also convenient as our GICv3
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// driver requires SRE. If only Memory mapped access is available we try to
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// drive the GIC as a v2.
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if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
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// Make sure System Register access is enabled (SRE). This depends on the
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// higher privilege level giving us permission, otherwise we will either
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// cause an exception here, or the write doesn't stick in which case we need
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// to fall back to the GICv2 MMIO interface.
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// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
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// at the same exception level.
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// It is the OS responsibility to set this bit.
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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if (!(IccSre & ICC_SRE_EL2_SRE)) {
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ArmGicV3SetControlSystemRegisterEnable (IccSre| ICC_SRE_EL2_SRE);
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IccSre = ArmGicV3GetControlSystemRegisterEnable ();
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}
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if (IccSre & ICC_SRE_EL2_SRE) {
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return ARM_GIC_ARCH_REVISION_3;
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}
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}
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return ARM_GIC_ARCH_REVISION_2;
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}
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