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audk/MdePkg/Include/RiscV64/RiscVasm.inc

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MdePkg: Implement RISC-V Cache Management Operations Implement Cache Management Operations (CMO) defined by RISC-V spec https://github.com/riscv/riscv-CMOs. Notes: 1. CMO only supports block based Operations. Meaning cache flush/invd/clean Operations are not available for the entire range. In that case we fallback on fence.i instructions. 2. Operations are implemented using Opcodes to make them compiler independent. binutils 2.39+ compilers support CMO instructions. Test: 1. Ensured correct instructions are refelecting in asm 2. Qemu implements basic support for CMO operations in that it allwos instructions without exceptions. Verified it works properly in that sense. 3. SG2042Pkg implements CMO-like instructions. It was verified that CpuFlushCpuDataCache works fine. This more of less confirms that framework is alright. 4. TODO: Once Silicon is available with exact instructions, we will further verify this. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Cc: Sunil V L <sunilvl@ventanamicro.com> Cc: Daniel Schaefer <git@danielschaefer.me> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Sunil V L <sunilvl@...> Reviewed-by: Jingyu Li <jingyu.li01@...>
2023-12-13 15:59:29 +01:00
/*
*
* RISC-V cache operation encoding.
* Copyright (c) 2023, Rivos Inc. All rights reserved.<BR>
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
*/
.macro RISCVCMOFLUSH
.word 0x25200f
.endm
.macro RISCVCMOINVALIDATE
.word 0x05200f
.endm
.macro RISCVCMOCLEAN
.word 0x15200f
.endm