2017-04-05 10:33:16 +02:00
|
|
|
/** @file
|
|
|
|
Features in MSR_IA32_FEATURE_CONTROL register.
|
|
|
|
|
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040
Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}
1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.
The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.
The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-16 05:57:30 +02:00
|
|
|
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
|
2019-04-04 01:07:22 +02:00
|
|
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
2017-04-05 10:33:16 +02:00
|
|
|
|
|
|
|
**/
|
|
|
|
|
|
|
|
#include "CpuCommonFeatures.h"
|
|
|
|
|
|
|
|
/**
|
|
|
|
Detects if VMX feature supported on current processor.
|
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
|
|
|
|
|
|
|
@retval TRUE VMX feature is supported.
|
|
|
|
@retval FALSE VMX feature is not supported.
|
|
|
|
|
|
|
|
@note This service could be called by BSP/APs.
|
|
|
|
**/
|
|
|
|
BOOLEAN
|
|
|
|
EFIAPI
|
|
|
|
VmxSupport (
|
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
|
|
|
IN VOID *ConfigData OPTIONAL
|
|
|
|
)
|
|
|
|
{
|
|
|
|
return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX == 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2017-07-11 04:07:36 +02:00
|
|
|
Initializes VMX feature to specific state.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
2017-07-11 04:07:36 +02:00
|
|
|
@param[in] State If TRUE, then the VMX feature must be enabled.
|
|
|
|
If FALSE, then the VMX feature must be disabled.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
2017-07-11 04:07:36 +02:00
|
|
|
@retval RETURN_SUCCESS VMX feature is initialized.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
|
|
|
@note This service could be called by BSP only.
|
|
|
|
**/
|
|
|
|
RETURN_STATUS
|
|
|
|
EFIAPI
|
2017-07-11 04:07:36 +02:00
|
|
|
VmxInitialize (
|
2017-04-05 10:33:16 +02:00
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
2021-12-03 03:01:00 +01:00
|
|
|
IN VOID *ConfigData OPTIONAL,
|
2017-04-05 10:33:16 +02:00
|
|
|
IN BOOLEAN State
|
|
|
|
)
|
|
|
|
{
|
2018-10-17 03:24:05 +02:00
|
|
|
//
|
|
|
|
// The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL is core for
|
|
|
|
// below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
|
|
|
|
// core.
|
|
|
|
//
|
|
|
|
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
|
|
|
|
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
|
|
|
|
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
|
|
|
|
{
|
|
|
|
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
|
|
|
|
return RETURN_SUCCESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040
Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}
1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.
The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.
The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-16 05:57:30 +02:00
|
|
|
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
Msr,
|
|
|
|
MSR_IA32_FEATURE_CONTROL,
|
|
|
|
MSR_IA32_FEATURE_CONTROL_REGISTER,
|
|
|
|
Bits.EnableVmxOutsideSmx,
|
|
|
|
(State) ? 1 : 0
|
|
|
|
);
|
|
|
|
|
2017-04-05 10:33:16 +02:00
|
|
|
return RETURN_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Detects if Lock Feature Control Register feature supported on current processor.
|
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
|
|
|
|
|
|
|
@retval TRUE Lock Feature Control Register feature is supported.
|
|
|
|
@retval FALSE Lock Feature Control Register feature is not supported.
|
|
|
|
|
|
|
|
@note This service could be called by BSP/APs.
|
|
|
|
**/
|
|
|
|
BOOLEAN
|
|
|
|
EFIAPI
|
|
|
|
LockFeatureControlRegisterSupport (
|
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
|
|
|
IN VOID *ConfigData OPTIONAL
|
|
|
|
)
|
|
|
|
{
|
|
|
|
return TRUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Initializes Lock Feature Control Register feature to specific state.
|
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
|
|
|
@param[in] State If TRUE, then the Lock Feature Control Register feature must be enabled.
|
|
|
|
If FALSE, then the Lock Feature Control Register feature must be disabled.
|
|
|
|
|
|
|
|
@retval RETURN_SUCCESS Lock Feature Control Register feature is initialized.
|
|
|
|
|
|
|
|
@note This service could be called by BSP only.
|
|
|
|
**/
|
|
|
|
RETURN_STATUS
|
|
|
|
EFIAPI
|
|
|
|
LockFeatureControlRegisterInitialize (
|
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
2021-12-03 03:01:00 +01:00
|
|
|
IN VOID *ConfigData OPTIONAL,
|
2017-04-05 10:33:16 +02:00
|
|
|
IN BOOLEAN State
|
|
|
|
)
|
|
|
|
{
|
2018-10-17 03:24:05 +02:00
|
|
|
//
|
|
|
|
// The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
|
|
|
|
// below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
|
|
|
|
// core.
|
|
|
|
//
|
|
|
|
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
|
|
|
|
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
|
|
|
|
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
|
|
|
|
{
|
|
|
|
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
|
|
|
|
return RETURN_SUCCESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040
Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}
1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.
The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.
The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-16 05:57:30 +02:00
|
|
|
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
Msr,
|
|
|
|
MSR_IA32_FEATURE_CONTROL,
|
|
|
|
MSR_IA32_FEATURE_CONTROL_REGISTER,
|
|
|
|
Bits.Lock,
|
|
|
|
1
|
|
|
|
);
|
|
|
|
|
2017-04-05 10:33:16 +02:00
|
|
|
return RETURN_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
Detects if SMX feature supported on current processor.
|
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
|
|
|
|
|
|
|
@retval TRUE SMX feature is supported.
|
|
|
|
@retval FALSE SMX feature is not supported.
|
|
|
|
|
|
|
|
@note This service could be called by BSP/APs.
|
|
|
|
**/
|
|
|
|
BOOLEAN
|
|
|
|
EFIAPI
|
|
|
|
SmxSupport (
|
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
|
|
|
IN VOID *ConfigData OPTIONAL
|
|
|
|
)
|
|
|
|
{
|
|
|
|
return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX == 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2017-07-11 04:07:36 +02:00
|
|
|
Initializes SMX feature to specific state.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
|
|
|
@param[in] ProcessorNumber The index of the CPU executing this function.
|
|
|
|
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
|
|
|
|
structure for the CPU executing this function.
|
|
|
|
@param[in] ConfigData A pointer to the configuration buffer returned
|
|
|
|
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
|
|
|
|
CPU_FEATURE_GET_CONFIG_DATA was not provided in
|
|
|
|
RegisterCpuFeature().
|
2017-07-11 04:07:36 +02:00
|
|
|
@param[in] State If TRUE, then SMX feature must be enabled.
|
|
|
|
If FALSE, then SMX feature must be disabled.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
2017-07-11 04:07:36 +02:00
|
|
|
@retval RETURN_SUCCESS SMX feature is initialized.
|
|
|
|
@retval RETURN_UNSUPPORTED VMX not initialized.
|
2017-04-05 10:33:16 +02:00
|
|
|
|
|
|
|
@note This service could be called by BSP only.
|
|
|
|
**/
|
|
|
|
RETURN_STATUS
|
|
|
|
EFIAPI
|
2017-07-11 04:07:36 +02:00
|
|
|
SmxInitialize (
|
2017-04-05 10:33:16 +02:00
|
|
|
IN UINTN ProcessorNumber,
|
|
|
|
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
|
2021-12-03 03:01:00 +01:00
|
|
|
IN VOID *ConfigData OPTIONAL,
|
2017-04-05 10:33:16 +02:00
|
|
|
IN BOOLEAN State
|
|
|
|
)
|
|
|
|
{
|
2017-07-11 04:07:36 +02:00
|
|
|
RETURN_STATUS Status;
|
|
|
|
|
2018-10-17 03:24:05 +02:00
|
|
|
//
|
|
|
|
// The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
|
|
|
|
// below processor type, only program MSR_IA32_FEATURE_CONTROL for thread 0 in each
|
|
|
|
// core.
|
|
|
|
//
|
|
|
|
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
|
|
|
|
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
|
|
|
|
{
|
|
|
|
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
|
|
|
|
return RETURN_SUCCESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-11 04:07:36 +02:00
|
|
|
Status = RETURN_SUCCESS;
|
|
|
|
|
|
|
|
if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {
|
|
|
|
DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));
|
|
|
|
State = FALSE;
|
|
|
|
Status = RETURN_UNSUPPORTED;
|
|
|
|
}
|
2017-04-05 10:33:16 +02:00
|
|
|
|
2019-12-23 07:55:37 +01:00
|
|
|
CPU_REGISTER_TABLE_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
ControlRegister,
|
|
|
|
4,
|
|
|
|
IA32_CR4,
|
|
|
|
Bits.SMXE,
|
|
|
|
(State) ? 1 : 0
|
|
|
|
)
|
|
|
|
|
UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040
Below code is current implementation:
if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_FEATURE_CONTROL,
MSR_IA32_FEATURE_CONTROL_REGISTER,
Bits.Lock,
1
);
}
1. In first normal boot, the Bits.Lock is 0, 1 will be added
into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
the Bits.Lock is 1, so it will not be added into the register
table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
not added in register table, so it's still 0 after resume. This
is not an expect behavior. The expect value is the value should
always 1 after booting or resuming from S3.
The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
the register table.
2. Some MSRs may reserve their value during warm reboot.
The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-16 05:57:30 +02:00
|
|
|
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
Msr,
|
|
|
|
MSR_IA32_FEATURE_CONTROL,
|
|
|
|
MSR_IA32_FEATURE_CONTROL_REGISTER,
|
|
|
|
Bits.SenterLocalFunctionEnables,
|
|
|
|
(State) ? 0x7F : 0
|
|
|
|
);
|
|
|
|
|
|
|
|
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
Msr,
|
|
|
|
MSR_IA32_FEATURE_CONTROL,
|
|
|
|
MSR_IA32_FEATURE_CONTROL_REGISTER,
|
|
|
|
Bits.SenterGlobalEnable,
|
|
|
|
(State) ? 1 : 0
|
|
|
|
);
|
|
|
|
|
|
|
|
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
|
|
|
|
ProcessorNumber,
|
|
|
|
Msr,
|
|
|
|
MSR_IA32_FEATURE_CONTROL,
|
|
|
|
MSR_IA32_FEATURE_CONTROL_REGISTER,
|
|
|
|
Bits.EnableVmxInsideSmx,
|
|
|
|
(State) ? 1 : 0
|
|
|
|
);
|
|
|
|
|
2017-07-11 04:07:36 +02:00
|
|
|
return Status;
|
2017-04-05 10:33:16 +02:00
|
|
|
}
|