mirror of https://github.com/acidanthera/audk.git
87 lines
2.8 KiB
C
87 lines
2.8 KiB
C
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/** @file
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Register initialization table for Ich.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "CommonHeader.h"
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VOID
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PlatformInitQNCRegs (
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VOID
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)
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{
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//
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// All devices on bus 0.
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// Device 0:
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// FNC 0: Host Bridge
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// Device 20:
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// FNC 0: IOSF2AHB Bridge
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// Device 21:
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// FNC 0: IOSF2AHB Bridge
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// Device 23:
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// FNC 0: PCIe Port 0
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// Device 24:
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// FNC 0: PCIe Port 1
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// Device 31:
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// FNC 0: PCI-LPC Bridge
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//
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S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_FWH_BIOS_DEC),
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B_QNC_LPC_FWH_BIOS_DEC_F0 | B_QNC_LPC_FWH_BIOS_DEC_F8 |
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B_QNC_LPC_FWH_BIOS_DEC_E0 | B_QNC_LPC_FWH_BIOS_DEC_E8 |
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B_QNC_LPC_FWH_BIOS_DEC_D0 | B_QNC_LPC_FWH_BIOS_DEC_D8 |
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B_QNC_LPC_FWH_BIOS_DEC_C0 | B_QNC_LPC_FWH_BIOS_DEC_C8
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);
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//
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// Program SCI Interrupt for IRQ9
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//
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S3PciWrite8 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_ACTL),
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V_QNC_LPC_ACTL_SCIS_IRQ9
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);
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//
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// Program Quark Interrupt Route Registers
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//
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S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT0IR,
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PcdGet16(PcdQuarkAgent0IR)
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);
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S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT1IR,
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PcdGet16(PcdQuarkAgent1IR)
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);
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S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT2IR,
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PcdGet16(PcdQuarkAgent2IR)
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);
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S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT3IR,
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PcdGet16(PcdQuarkAgent3IR)
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);
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//
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// Program SVID and SID for QNC PCI devices. In order to boost performance, we
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// combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE. The programmed LPC SVID
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// will reflect on all internal devices's SVID registers
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//
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S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID),
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(UINT32)(V_INTEL_VENDOR_ID + (QUARK_V_LPC_DEVICE_ID_0 << 16))
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);
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//
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// Write once on Element Self Description Register before OS boot
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//
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QNCMmio32And (PcdGet64(PcdRcbaMmioBaseAddress), 0x04, 0xFF00FFFF);
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return;
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}
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