mirror of https://github.com/acidanthera/audk.git
79 lines
3.8 KiB
C
79 lines
3.8 KiB
C
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/** @file
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Header file of Serial port hardware definition.
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Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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This software and associated documentation
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(if any) is furnished under a license and may only be used or
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copied in accordance with the terms of the license. Except as
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permitted by such license, no part of this software or
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documentation may be reproduced, stored in a retrieval system, or
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transmitted in any form or by any means without the express written
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consent of Intel Corporation.
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Module Name: PlatformSerialPortLib.h
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**/
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#ifndef _SIO_INIT_H_
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#define _SIO_INIT_H_
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#define WPCN381U_CONFIG_INDEX 0x2E
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#define WPCN381U_CONFIG_DATA 0x2F
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#define WPCN381U_CONFIG_INDEX1 0x164E
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#define WPCN381U_CONFIG_DATA1 0x164F
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#define WPCN381U_CHIP_ID 0xF4
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#define WDCP376_CHIP_ID 0xF1
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//
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// SIO Logical Devices Numbers
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//
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#define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller
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#define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller
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#define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller
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#define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller
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#define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller
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#define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller
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#define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source
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#define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO
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//
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// SIO Registers Layout
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//
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#define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address
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#define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address
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#define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address
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#define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address
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#define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address
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#define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address
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#define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address
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#define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address
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#define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address
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//
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// SIO Activation Values
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//
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#define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device
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#define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device
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//
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// SIO GPIO
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//
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#define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address
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//
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// SIO Serial Port Settings
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//
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#define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
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#define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
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#endif
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