2013-01-25 12:28:06 +01:00
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/** @file
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Library/IoLib.h>
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#include <Library/ArmPlatformLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/SerialPortLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL301Axi.h>
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#include <Drivers/SP804Timer.h>
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#include <Ppi/ArmMpCoreInfo.h>
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#include <ArmPlatform.h>
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#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
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ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
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{
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// Cluster 0, Core 0
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0x0, 0x0,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
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(UINT64)0xFFFFFFFF
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},
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{
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// Cluster 0, Core 1
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0x0, 0x1,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
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(UINT64)0xFFFFFFFF
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},
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{
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// Cluster 0, Core 2
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0x0, 0x2,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
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(UINT64)0xFFFFFFFF
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},
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{
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// Cluster 0, Core 3
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0x0, 0x3,
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// MP Core MailBox Set/Get/Clear Addresses and Clear Value
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
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(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
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(UINT64)0xFFFFFFFF
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}
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};
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// DDR2 timings
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PL341_DMC_CONFIG DDRTimings = {
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.MaxChip = 1,
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.IsUserCfg = TRUE,
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.User0Cfg = 0x7C924924,
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.User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
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.HasQos = TRUE,
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.RefreshPeriod = 0x3D0,
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.CasLatency = 0x8,
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.WriteLatency = 0x3,
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.t_mrd = 0x2,
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.t_ras = 0xA,
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.t_rc = 0xE,
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.t_rcd = 0x104,
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.t_rfc = 0x2f32,
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.t_rp = 0x14,
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.t_rrd = 0x2,
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.t_wr = 0x4,
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.t_wtr = 0x2,
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.t_xp = 0x2,
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.t_xsr = 0xC8,
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.t_esr = 0x14,
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.MemoryCfg = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
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DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
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.MemoryCfg2 = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
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DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
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.MemoryCfg3 = 0x00000001,
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.ChipCfg0 = 0x00010000,
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.t_faw = 0x00000A0D,
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.ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
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.ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
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};
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/**
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Return the current Boot Mode
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This function returns the boot reason on the platform
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@return Return the current Boot Mode of the platform
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**/
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EFI_BOOT_MODE
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ArmPlatformGetBootMode (
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VOID
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)
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{
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if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
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return BOOT_WITH_FULL_CONFIGURATION;
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} else {
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return BOOT_ON_S2_RESUME;
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}
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}
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/**
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Initialize controllers that must setup in the normal world
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This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
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in the PEI phase.
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**/
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RETURN_STATUS
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ArmPlatformInitialize (
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IN UINTN MpId
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)
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{
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if (!IS_PRIMARY_CORE(MpId)) {
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return RETURN_SUCCESS;
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}
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// Configure periodic timer (TIMER0) for 1MHz operation
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
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// Configure 1MHz clock
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MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
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// configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
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// Configure SP810 to use 1MHz clock and disable
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MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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return RETURN_SUCCESS;
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}
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/**
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Initialize the system (or sometimes called permanent) memory
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This memory is generally represented by the DRAM.
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**/
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VOID
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ArmPlatformInitializeSystemMemory (
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VOID
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)
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{
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UINT32 Value;
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// Memory Map remapping
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if (FeaturePcdGet(PcdNorFlashRemapping)) {
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SerialPrint ("Secure ROM at 0x0\n\r");
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} else {
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Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
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// Remap the DRAM to 0x0
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MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
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}
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PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
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PL301AxiInit(ARM_VE_FAXI_BASE);
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}
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EFI_STATUS
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PrePeiCoreGetMpCoreInfo (
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OUT UINTN *CoreCount,
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OUT ARM_CORE_INFO **ArmCoreTable
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)
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{
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*CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
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*ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
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return EFI_SUCCESS;
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}
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// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
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EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
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ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
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EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&mArmMpCoreInfoPpiGuid,
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&mMpCoreInfoPpi
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}
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};
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VOID
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ArmPlatformGetPlatformPpiList (
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OUT UINTN *PpiListSize,
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OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
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)
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{
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*PpiListSize = sizeof(gPlatformPpiTable);
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*PpiList = gPlatformPpiTable;
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}
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