2015-01-12 10:37:20 +01:00
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/**************************************************************************;
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;* *;
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;* *;
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;* Intel Corporation - ACPI Reference Code for the Baytrail *;
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;* Family of Customer Reference Boards. *;
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;* *;
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;* *;
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2016-06-08 08:24:16 +02:00
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;* Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved *;
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2015-01-12 10:37:20 +01:00
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;
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; This program and the accompanying materials are licensed and made available under
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; the terms and conditions of the BSD License that accompanies this distribution.
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; The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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;* *;
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;* *;
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;**************************************************************************/
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// Define a Global region of ACPI NVS Region that may be used for any
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// type of implementation. The starting offset and size will be fixed
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// up by the System BIOS during POST. Note that the Size must be a word
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// in size to be fixed up correctly.
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OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55)
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Field(GNVS,AnyAcc,Lock,Preserve)
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{
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Offset(0), // Miscellaneous Dynamic Registers:
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OSYS, 16, // (00) Operating System
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, 8, // (02)
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, 8, // (03)
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, 8, // (04)
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, 8, // (05)
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, 8, // (06)
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, 8, // (07)
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, 8, // (08)
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, 8, // (09)
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, 8, // (10)
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P80D, 32, // (11) Port 80 Debug Port Value
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LIDS, 8, // (15) Lid State (Lid Open = 1)
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, 8, // (16)
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, 8, // (17)
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Offset(18), // Thermal Policy Registers:
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, 8, // (18)
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, 8, // (19)
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ACTT, 8, // (20) Active Trip Point
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PSVT, 8, // (21) Passive Trip Point
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TC1V, 8, // (22) Passive Trip Point TC1 Value
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TC2V, 8, // (23) Passive Trip Point TC2 Value
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TSPV, 8, // (24) Passive Trip Point TSP Value
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CRTT, 8, // (25) Critical Trip Point
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DTSE, 8, // (26) Digital Thermal Sensor Enable
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DTS1, 8, // (27) Digital Thermal Sensor 1 Reading
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DTS2, 8, // (28) Digital Thermal Sensor 2 Reading
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DTSF, 8, // (29) DTS SMI Function Call
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Offset(30), // Battery Support Registers:
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, 8, // (30)
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, 8, // (31)
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, 8, // (32)
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, 8, // (33)
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, 8, // (34)
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, 8, // (35)
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, 8, // (36)
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Offset(40), // CPU Identification Registers:
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APIC, 8, // (40) APIC Enabled by SBIOS (APIC Enabled = 1)
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MPEN, 8, // (41) Number of Logical Processors if MP Enabled != 0
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, 8, // (42)
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, 8, // (43)
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, 8, // (44)
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, 32, // (45)
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Offset(50), // SIO CMOS Configuration Registers:
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, 8, // (50)
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, 8, // (51)
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, 8, // (52)
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, 8, // (53)
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, 8, // (54)
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, 8, // (55)
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, 8, // (56)
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, 8, // (57)
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, 8, // (58)
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Offset(60), // Internal Graphics Registers:
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, 8, // (60)
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, 8, // (61)
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CADL, 8, // (62) Current Attached Device List
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, 8, // (63)
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CSTE, 16, // (64) Current Display State
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NSTE, 16, // (66) Next Display State
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, 16, // (68)
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NDID, 8, // (70) Number of Valid Device IDs
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DID1, 32, // (71) Device ID 1
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DID2, 32, // (75) Device ID 2
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DID3, 32, // (79) Device ID 3
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DID4, 32, // (83) Device ID 4
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DID5, 32, // (87) Device ID 5
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, 32, // (91)
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, 8, // (95) Fifth byte of AKSV (mannufacturing mode)
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Offset(103), // Backlight Control Registers:
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, 8, // (103)
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BRTL, 8, // (104) Brightness Level Percentage
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Offset(105), // Ambiant Light Sensor Registers:
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, 8, // (105)
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, 8, // (106)
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LLOW, 8, // (107) LUX Low Value
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, 8, // (108)
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Offset(110), // EMA Registers:
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, 8, // (110)
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, 16, // (111)
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, 16, // (113)
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Offset(116), // MEF Registers:
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, 8, // (116) MEF Enable
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Offset(117), // PCIe Dock:
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, 8, // (117)
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Offset(120), // TPM Registers:
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, 8, // (120)
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, 8, // (121)
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, 8, // (122)
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, 8, // (123)
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, 32, // (124)
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, 8, // (125)
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, 8, // (129)
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Offset(130), //
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, 56, // (130)
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, 56, // (137)
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, 8, // (144)
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, 56, // (145)
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Offset(170), // IGD OpRegion/Software SCI base address
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ASLB, 32, // (170) IGD OpRegion base address
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Offset(174), // IGD OpRegion/Software SCI shared data
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IBTT, 8, // (174) IGD Boot Display Device
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IPAT, 8, // (175) IGD Panel Type CMOs option
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ITVF, 8, // (176) IGD TV Format CMOS option
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ITVM, 8, // (177) IGD TV Minor Format CMOS option
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IPSC, 8, // (178) IGD Panel Scaling
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IBLC, 8, // (179) IGD BLC Configuration
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IBIA, 8, // (180) IGD BIA Configuration
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ISSC, 8, // (181) IGD SSC Configuration
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I409, 8, // (182) IGD 0409 Modified Settings Flag
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I509, 8, // (183) IGD 0509 Modified Settings Flag
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I609, 8, // (184) IGD 0609 Modified Settings Flag
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I709, 8, // (185) IGD 0709 Modified Settings Flag
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IDMM, 8, // (186) IGD DVMT Mode
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IDMS, 8, // (187) IGD DVMT Memory Size
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IF1E, 8, // (188) IGD Function 1 Enable
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HVCO, 8, // (189) HPLL VCO
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NXD1, 32, // (190) Next state DID1 for _DGS
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NXD2, 32, // (194) Next state DID2 for _DGS
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NXD3, 32, // (198) Next state DID3 for _DGS
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NXD4, 32, // (202) Next state DID4 for _DGS
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NXD5, 32, // (206) Next state DID5 for _DGS
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NXD6, 32, // (210) Next state DID6 for _DGS
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NXD7, 32, // (214) Next state DID7 for _DGS
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NXD8, 32, // (218) Next state DID8 for _DGS
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GSMI, 8, // (222) GMCH SMI/SCI mode (0=SCI)
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PAVP, 8, // (223) IGD PAVP data
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Offset(225),
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OSCC, 8, // (225) PCIE OSC Control
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NEXP, 8, // (226) Native PCIE Setup Value
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Offset(235), // Global Variables
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DSEN, 8, // (235) _DOS Display Support Flag.
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ECON, 8, // (236) Embedded Controller Availability Flag.
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GPIC, 8, // (237) Global IOAPIC/8259 Interrupt Mode Flag.
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CTYP, 8, // (238) Global Cooling Type Flag.
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L01C, 8, // (239) Global L01 Counter.
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VFN0, 8, // (240) Virtual Fan0 Status.
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VFN1, 8, // (241) Virtual Fan1 Status.
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Offset(256),
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NVGA, 32, // (256) NVIG opregion address
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NVHA, 32, // (260) NVHM opregion address
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AMDA, 32, // (264) AMDA opregion address
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DID6, 32, // (268) Device ID 6
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DID7, 32, // (272) Device ID 7
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DID8, 32, // (276) Device ID 8
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Offset(332),
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USEL, 8, // (332) UART Selection
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PU1E, 8, // (333) PCU UART 1 Enabled
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PU2E, 8, // (334) PCU UART 2 Enabled
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LPE0, 32, // (335) LPE Bar0
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LPE1, 32, // (339) LPE Bar1
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LPE2, 32, // (343) LPE Bar2
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Offset(347),
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, 8, // (347)
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, 8, // (348)
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PFLV, 8, // (349) Platform Flavor
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Offset(351),
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ICNF, 8, // (351) ISCT / AOAC Configuration
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XHCI, 8, // (352) xHCI controller mode
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PMEN, 8, // (353) PMIC enable/disable
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LPEE, 8, // (354) LPE enable/disable
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ISPA, 32, // (355) ISP Base Addr
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ISPD, 8, // (359) ISP Device Selection 0: Disabled; 1: PCI Device 2; 2: PCI Device 3
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offset(360), // ((4+8+6)*4+2)*4=296
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//
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// Lpss controllers
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//
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PCIB, 32,
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PCIT, 32,
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D10A, 32, //DMA1
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D10L, 32,
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D11A, 32,
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D11L, 32,
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P10A, 32, // PWM1
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P10L, 32,
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P11A, 32,
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P11L, 32,
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P20A, 32, // PWM2
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P20L, 32,
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P21A, 32,
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P21L, 32,
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U10A, 32, // UART1
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U10L, 32,
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U11A, 32,
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U11L, 32,
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U20A, 32, // UART2
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U20L, 32,
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U21A, 32,
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U21L, 32,
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SP0A, 32, // SPI
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SP0L, 32,
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SP1A, 32,
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SP1L, 32,
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D20A, 32, //DMA2
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D20L, 32,
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D21A, 32,
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D21L, 32,
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I10A, 32, // I2C1
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I10L, 32,
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I11A, 32,
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I11L, 32,
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I20A, 32, // I2C2
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I20L, 32,
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I21A, 32,
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I21L, 32,
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I30A, 32, // I2C3
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I30L, 32,
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I31A, 32,
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I31L, 32,
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I40A, 32, // I2C4
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I40L, 32,
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I41A, 32,
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I41L, 32,
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I50A, 32, // I2C5
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I50L, 32,
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I51A, 32,
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I51L, 32,
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I60A, 32, // I2C6
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I60L, 32,
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I61A, 32,
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I61L, 32,
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I70A, 32, // I2C7
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I70L, 32,
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I71A, 32,
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I71L, 32,
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//
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// Scc controllers
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//
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eM0A, 32, // EMMC
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eM0L, 32,
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eM1A, 32,
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eM1L, 32,
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SI0A, 32, // SDIO
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SI0L, 32,
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SI1A, 32,
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SI1L, 32,
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SD0A, 32, // SDCard
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SD0L, 32,
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SD1A, 32,
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SD1L, 32,
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MH0A, 32, //
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MH0L, 32,
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MH1A, 32,
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MH1L, 32,
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offset(656),
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SDRM, 8,
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offset(657),
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HLPS, 8, //(657) Hide Devices
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offset(658),
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OSEL, 8, //(658) OS Seletion - Windows/Android
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offset(659), // VLV1 DPTF
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SDP1, 8, //(659) An enumerated value corresponding to SKU
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DPTE, 8, //(660) DPTF Enable
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THM0, 8, //(661) System Thermal 0
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THM1, 8, //(662) System Thermal 1
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THM2, 8, //(663) System Thermal 2
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THM3, 8, //(664) System Thermal 3
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THM4, 8, //(665) System Thermal 3
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CHGR, 8, //(666) DPTF Changer Device
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DDSP, 8, //(667) DPTF Display Device
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DSOC, 8, //(668) DPTF SoC device
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DPSR, 8, //(669) DPTF Processor device
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DPCT, 32, //(670) DPTF Processor participant critical temperature
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DPPT, 32, //(674) DPTF Processor participant passive temperature
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DGC0, 32, //(678) DPTF Generic sensor0 participant critical temperature
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DGP0, 32, //(682) DPTF Generic sensor0 participant passive temperature
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DGC1, 32, //(686) DPTF Generic sensor1 participant critical temperature
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DGP1, 32, //(690) DPTF Generic sensor1 participant passive temperature
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DGC2, 32, //(694) DPTF Generic sensor2 participant critical temperature
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DGP2, 32, //(698) DPTF Generic sensor2 participant passive temperature
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DGC3, 32, //(702) DPTF Generic sensor3 participant critical temperature
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DGP3, 32, //(706) DPTF Generic sensor3 participant passive temperature
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DGC4, 32, //(710)DPTF Generic sensor3 participant critical temperature
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DGP4, 32, //(714)DPTF Generic sensor3 participant passive temperature
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DLPM, 8, //(718) DPTF Current low power mode setting
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DSC0, 32, //(719) DPTF Critical threshold0 for SCU
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DSC1, 32, //(723) DPTF Critical threshold1 for SCU
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DSC2, 32, //(727) DPTF Critical threshold2 for SCU
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DSC3, 32, //(731) DPTF Critical threshold3 for SCU
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DSC4, 32, //(735) DPTF Critical threshold3 for SCU
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DDBG, 8, //(739) DPTF Super Debug option. 0 - Disabled, 1 - Enabled
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LPOE, 32, //(740) DPTF LPO Enable
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LPPS, 32, //(744) P-State start index
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LPST, 32, //(748) Step size
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LPPC, 32, //(752) Power control setting
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LPPF, 32, //(756) Performance control setting
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DPME, 8, //(760) DPTF DPPM enable/disable
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BCSL, 8, //(761) Battery charging solution 0-CLV 1-ULPMC
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NFCS, 8, //(762) NFCx Select 1: NFC1 2:NFC2
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PCIM, 8, //(763) EMMC device 0-ACPI mode, 1-PCI mode
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TPMA, 32, //(764)
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TPML, 32, //(768)
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ITSA, 8, //(772) I2C Touch Screen Address
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S0IX, 8, //(773) S0ix status
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SDMD, 8, //(774) SDIO Mode
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EMVR, 8, //(775) eMMC controller version
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BMBD, 32, //(776) BM Bound
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FSAS, 8, //(780) FSA Status
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BDID, 8, //(781) Board ID
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FBID, 8, //(782) FAB ID
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OTGM, 8, //(783) OTG mode
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STEP, 8, //(784) Stepping ID
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WITT, 8, //(785) Enable Test Device connected to I2C for WHCK test.
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SOCS, 8, //(786) provide the SoC stepping infomation
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AMTE, 8, //(787) Ambient Trip point change
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UTS, 8, //(788) Enable Test Device connected to URT for WHCK test.
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SCPE, 8, //(789) Allow higher performance on AC/USB - Enable/Disable
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Offset(792),
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EDPV, 8, //(792) Check for eDP display device
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DIDX, 32, //(793) Device ID for eDP device
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2015-11-10 08:47:29 +01:00
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IOT, 8, //(794) MinnowBoard Max JP1 is configured for MSFT IOT project.
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2016-06-21 05:05:30 +02:00
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BATT, 8, //(795) The Flag of RTC Battery Prensent.
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2016-06-08 08:24:16 +02:00
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LPAD, 8, //(796)
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2015-01-12 10:37:20 +01:00
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}
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