mirror of https://github.com/acidanthera/audk.git
123 lines
4.8 KiB
C
123 lines
4.8 KiB
C
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/** @file
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Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __ISP1761_USB_DXE_H__
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#define __ISP1761_USB_DXE_H__
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#define ISP1761_USB_BASE FixedPcdGet32 (PcdIsp1761BaseAddress)
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#define READ_REG32(Offset) MmioRead32 (ISP1761_USB_BASE + Offset)
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#define READ_REG16(Offset) (UINT16) READ_REG32 (Offset)
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#define WRITE_REG32(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, Val)
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#define WRITE_REG16(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
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#define WRITE_REG8(Offset, Val) MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
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// Max packet size in bytes (For Full Speed USB 64 is the only valid value)
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#define MAX_PACKET_SIZE_CONTROL 64
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#define MAX_PACKET_SIZE_BULK 512
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// 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer
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#define ISP1761_NUM_ENDPOINTS 16
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// Endpoint Indexes
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#define ISP1761_EP0SETUP 0x20
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#define ISP1761_EP0RX 0x00
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#define ISP1761_EP0TX 0x01
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#define ISP1761_EP1RX 0x02
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#define ISP1761_EP1TX 0x03
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// DcInterrupt bits
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#define ISP1761_DC_INTERRUPT_BRESET BIT0
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#define ISP1761_DC_INTERRUPT_SOF BIT1
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#define ISP1761_DC_INTERRUPT_PSOF BIT2
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#define ISP1761_DC_INTERRUPT_SUSP BIT3
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#define ISP1761_DC_INTERRUPT_RESUME BIT4
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#define ISP1761_DC_INTERRUPT_HS_STAT BIT5
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#define ISP1761_DC_INTERRUPT_DMA BIT6
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#define ISP1761_DC_INTERRUPT_VBUS BIT7
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#define ISP1761_DC_INTERRUPT_EP0SETUP BIT8
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#define ISP1761_DC_INTERRUPT_EP0RX BIT10
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#define ISP1761_DC_INTERRUPT_EP0TX BIT11
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#define ISP1761_DC_INTERRUPT_EP1RX BIT12
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#define ISP1761_DC_INTERRUPT_EP1TX BIT13
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// All valid peripheral controller interrupts
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#define ISP1761_DC_INTERRUPT_MASK 0x003FFFDFF
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#define ISP1761_ADDRESS 0x200
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#define ISP1761_ADDRESS_DEVEN BIT7
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#define ISP1761_MODE 0x20C
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#define ISP1761_MODE_DATA_BUS_WIDTH BIT8
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#define ISP1761_MODE_CLKAON BIT7
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#define ISP1761_MODE_SFRESET BIT4
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#define ISP1761_MODE_WKUPCS BIT2
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#define ISP1761_ENDPOINT_MAX_PACKET_SIZE 0x204
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#define ISP1761_ENDPOINT_TYPE 0x208
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#define ISP1761_ENDPOINT_TYPE_NOEMPKT BIT4
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#define ISP1761_ENDPOINT_TYPE_ENABLE BIT3
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#define ISP1761_INTERRUPT_CONFIG 0x210
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// Interrupt config value to only interrupt on ACK of IN and OUT tokens
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#define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6
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#define ISP1761_DC_INTERRUPT 0x218
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#define ISP1761_DC_INTERRUPT_ENABLE 0x214
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#define ISP1761_CTRL_FUNCTION 0x228
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#define ISP1761_CTRL_FUNCTION_VENDP BIT3
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#define ISP1761_CTRL_FUNCTION_DSEN BIT2
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#define ISP1761_CTRL_FUNCTION_STATUS BIT1
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#define ISP1761_DEVICE_UNLOCK 0x27C
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#define ISP1761_DEVICE_UNLOCK_MAGIC 0xAA37
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#define ISP1761_SW_RESET_REG 0x30C
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#define ISP1761_SW_RESET_ALL BIT0
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#define ISP1761_DEVICE_ID 0x370
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#define ISP1761_OTG_CTRL_SET 0x374
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#define ISP1761_OTG_CTRL_CLR OTG_CTRL_SET + 2
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#define ISP1761_OTG_CTRL_OTG_DISABLE BIT10
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#define ISP1761_OTG_CTRL_VBUS_CHRG BIT6
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#define ISP1761_OTG_CTRL_VBUS_DISCHRG BIT5
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#define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
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#define ISP1761_OTG_CTRL_DP_PULLDOWN BIT1
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#define ISP1761_OTG_CTRL_DP_PULLUP BIT0
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#define ISP1761_OTG_STATUS 0x378
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#define ISP1761_OTG_STATUS_B_SESS_END BIT7
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#define ISP1761_OTG_STATUS_A_B_SESS_VLD BIT1
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#define ISP1761_OTG_INTERRUPT_LATCH_SET 0x37C
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#define ISP1761_OTG_INTERRUPT_LATCH_CLR 0x37E
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#define ISP1761_OTG_INTERRUPT_ENABLE_RISE 0x384
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#define ISP1761_DMA_ENDPOINT_INDEX 0x258
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#define ISP1761_ENDPOINT_INDEX 0x22c
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#define ISP1761_DATA_PORT 0x220
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#define ISP1761_BUFFER_LENGTH 0x21c
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// Device ID Values
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#define PHILLIPS_VENDOR_ID_VAL 0x04cc
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#define ISP1761_PRODUCT_ID_VAL 0x1761
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#define ISP1761_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\
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PHILLIPS_VENDOR_ID_VAL)
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#endif //ifndef __ISP1761_USB_DXE_H__
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