2010-05-18 07:37:58 +02:00
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/** @file
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GCC inline implementation of BaseSynchronizationLib processor specific functions.
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2018-06-27 15:11:33 +02:00
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Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
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Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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2010-05-18 13:40:39 +02:00
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This program and the accompanying materials
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2010-05-18 07:37:58 +02:00
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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2010-06-25 23:56:02 +02:00
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http://opensource.org/licenses/bsd-license.php.
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2010-05-18 07:37:58 +02:00
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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/**
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Performs an atomic increment of an 32-bit unsigned integer.
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Performs an atomic increment of the 32-bit unsigned integer specified by
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Value and returns the incremented value. The increment operation must be
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2018-09-07 11:26:14 +02:00
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performed using MP safe mechanisms.
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2010-05-18 07:37:58 +02:00
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@param Value A pointer to the 32-bit value to increment.
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@return The incremented value.
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**/
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UINT32
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EFIAPI
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InternalSyncIncrement (
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IN volatile UINT32 *Value
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)
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{
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UINT32 Result;
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__asm__ __volatile__ (
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2018-09-07 11:26:14 +02:00
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"movl $1, %%eax \n\t"
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2010-05-18 07:37:58 +02:00
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"lock \n\t"
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MdePkg/BaseSynchronizationLib: fix XADD operands in GCC IA32/X64 assembly
Currently, "gcc-4.8.5-28.el7_5.1.x86_64" generates the following code for
me, from the XADD inline assembly added to "X64/GccInline.c" in commit
17634d026f96:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 00 lock xadd %eax,(%rax)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : "m" (*Value) // %2
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
>
The MOV $0X1,%EAX instruction corrupts the address of Value in %RAX before
we reach the XADD instruction. In fact, it makes no sense for XADD to use
%EAX as source operand and (%RAX) as destination operand at the same time.
The XADD instruction's destination operand is a read-write operand. The
GCC documentation states:
> The ordinary output operands must be write-only; GCC will assume that
> the values in these operands before the instruction are dead and need
> not be generated. Extended asm supports input-output or read-write
> operands. Use the constraint character `+' to indicate such an operand
> and list it with the output operands. You should only use read-write
> operands when the constraints for the operand (or the operand in which
> only some of the bits are to be changed) allow a register.
(The above is intentionally quoted from the oldest GCC release that edk2
supports, namely gcc-4.4:
<https://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Extended-Asm.html>.)
Fix the operand list accordingly.
With the patch applied, I get:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 02 lock xadd %eax,(%rdx)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : // no inputs that aren't also outputs
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
Note that some other bugs remain in
"BaseSynchronizationLib/*/GccInline.c"; those should be addressed later,
under <https://bugzilla.tianocore.org/show_bug.cgi?id=1208>.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1207
Fixes: 17634d026f968c404b039a8d8431b6389dd396ea
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-09-25 16:58:15 +02:00
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"xadd %%eax, %1 \n\t"
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2018-09-29 20:18:34 +02:00
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"inc %%eax \n\t"
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2010-05-18 07:37:58 +02:00
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: "=a" (Result), // %0
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MdePkg/BaseSynchronizationLib: fix XADD operands in GCC IA32/X64 assembly
Currently, "gcc-4.8.5-28.el7_5.1.x86_64" generates the following code for
me, from the XADD inline assembly added to "X64/GccInline.c" in commit
17634d026f96:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 00 lock xadd %eax,(%rax)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : "m" (*Value) // %2
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
>
The MOV $0X1,%EAX instruction corrupts the address of Value in %RAX before
we reach the XADD instruction. In fact, it makes no sense for XADD to use
%EAX as source operand and (%RAX) as destination operand at the same time.
The XADD instruction's destination operand is a read-write operand. The
GCC documentation states:
> The ordinary output operands must be write-only; GCC will assume that
> the values in these operands before the instruction are dead and need
> not be generated. Extended asm supports input-output or read-write
> operands. Use the constraint character `+' to indicate such an operand
> and list it with the output operands. You should only use read-write
> operands when the constraints for the operand (or the operand in which
> only some of the bits are to be changed) allow a register.
(The above is intentionally quoted from the oldest GCC release that edk2
supports, namely gcc-4.4:
<https://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Extended-Asm.html>.)
Fix the operand list accordingly.
With the patch applied, I get:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 02 lock xadd %eax,(%rdx)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : // no inputs that aren't also outputs
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
Note that some other bugs remain in
"BaseSynchronizationLib/*/GccInline.c"; those should be addressed later,
under <https://bugzilla.tianocore.org/show_bug.cgi?id=1208>.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1207
Fixes: 17634d026f968c404b039a8d8431b6389dd396ea
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-09-25 16:58:15 +02:00
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"+m" (*Value) // %1
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: // no inputs that aren't also outputs
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2010-05-18 07:37:58 +02:00
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: "memory",
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"cc"
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);
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2018-06-27 15:11:33 +02:00
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return Result;
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2010-05-18 07:37:58 +02:00
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}
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/**
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Performs an atomic decrement of an 32-bit unsigned integer.
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Performs an atomic decrement of the 32-bit unsigned integer specified by
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Value and returns the decremented value. The decrement operation must be
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2018-09-07 11:26:14 +02:00
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performed using MP safe mechanisms.
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2010-05-18 07:37:58 +02:00
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@param Value A pointer to the 32-bit value to decrement.
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@return The decremented value.
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**/
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UINT32
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EFIAPI
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InternalSyncDecrement (
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IN volatile UINT32 *Value
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)
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{
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UINT32 Result;
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2018-06-27 15:11:33 +02:00
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2010-05-18 07:37:58 +02:00
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__asm__ __volatile__ (
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2018-09-07 11:26:14 +02:00
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"movl $-1, %%eax \n\t"
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"lock \n\t"
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MdePkg/BaseSynchronizationLib: fix XADD operands in GCC IA32/X64 assembly
Currently, "gcc-4.8.5-28.el7_5.1.x86_64" generates the following code for
me, from the XADD inline assembly added to "X64/GccInline.c" in commit
17634d026f96:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 00 lock xadd %eax,(%rax)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : "m" (*Value) // %2
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
>
The MOV $0X1,%EAX instruction corrupts the address of Value in %RAX before
we reach the XADD instruction. In fact, it makes no sense for XADD to use
%EAX as source operand and (%RAX) as destination operand at the same time.
The XADD instruction's destination operand is a read-write operand. The
GCC documentation states:
> The ordinary output operands must be write-only; GCC will assume that
> the values in these operands before the instruction are dead and need
> not be generated. Extended asm supports input-output or read-write
> operands. Use the constraint character `+' to indicate such an operand
> and list it with the output operands. You should only use read-write
> operands when the constraints for the operand (or the operand in which
> only some of the bits are to be changed) allow a register.
(The above is intentionally quoted from the oldest GCC release that edk2
supports, namely gcc-4.4:
<https://gcc.gnu.org/onlinedocs/gcc-4.4.7/gcc/Extended-Asm.html>.)
Fix the operand list accordingly.
With the patch applied, I get:
> 0000000000004383 <InternalSyncIncrement>:
> UINT32
> EFIAPI
> InternalSyncIncrement (
> IN volatile UINT32 *Value
> )
> {
> 4383: 55 push %rbp
> 4384: 48 89 e5 mov %rsp,%rbp
> 4387: 48 83 ec 10 sub $0x10,%rsp
> 438b: 48 89 4d 10 mov %rcx,0x10(%rbp)
> UINT32 Result;
>
> __asm__ __volatile__ (
> 438f: 48 8b 55 10 mov 0x10(%rbp),%rdx
> 4393: 48 8b 45 10 mov 0x10(%rbp),%rax
> 4397: b8 01 00 00 00 mov $0x1,%eax
> 439c: f0 0f c1 02 lock xadd %eax,(%rdx)
> 43a0: ff c0 inc %eax
> 43a2: 89 45 fc mov %eax,-0x4(%rbp)
> : // no inputs that aren't also outputs
> : "memory",
> "cc"
> );
>
> return Result;
> 43a5: 8b 45 fc mov -0x4(%rbp),%eax
> }
> 43a8: c9 leaveq
> 43a9: c3 retq
Note that some other bugs remain in
"BaseSynchronizationLib/*/GccInline.c"; those should be addressed later,
under <https://bugzilla.tianocore.org/show_bug.cgi?id=1208>.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1207
Fixes: 17634d026f968c404b039a8d8431b6389dd396ea
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-09-25 16:58:15 +02:00
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"xadd %%eax, %1 \n\t"
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2018-09-29 20:18:34 +02:00
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"dec %%eax \n\t"
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: "=a" (Result), // %0
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"+m" (*Value) // %1
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: // no inputs that aren't also outputs
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2010-05-18 07:37:58 +02:00
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: "memory",
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"cc"
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);
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2018-06-27 15:11:33 +02:00
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2010-05-18 07:37:58 +02:00
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return Result;
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}
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2015-02-28 21:31:54 +01:00
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/**
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Performs an atomic compare exchange operation on a 16-bit unsigned integer.
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Performs an atomic compare exchange operation on the 16-bit unsigned integer
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specified by Value. If Value is equal to CompareValue, then Value is set to
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ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
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then Value is returned. The compare exchange operation must be performed using
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MP safe mechanisms.
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@param Value A pointer to the 16-bit value for the compare exchange
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operation.
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@param CompareValue 16-bit value used in compare operation.
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@param ExchangeValue 16-bit value used in exchange operation.
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@return The original *Value before exchange.
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**/
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UINT16
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EFIAPI
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InternalSyncCompareExchange16 (
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IN OUT volatile UINT16 *Value,
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IN UINT16 CompareValue,
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IN UINT16 ExchangeValue
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)
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{
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__asm__ __volatile__ (
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"lock \n\t"
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2018-09-29 21:22:57 +02:00
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"cmpxchgw %2, %1 \n\t"
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: "+a" (CompareValue), // %0
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"+m" (*Value) // %1
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: "r" (ExchangeValue) // %2
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2015-02-28 21:31:54 +01:00
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: "memory",
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"cc"
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);
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return CompareValue;
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}
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2010-05-18 07:37:58 +02:00
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/**
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Performs an atomic compare exchange operation on a 32-bit unsigned integer.
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Performs an atomic compare exchange operation on the 32-bit unsigned integer
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|
specified by Value. If Value is equal to CompareValue, then Value is set to
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ExchangeValue and CompareValue is returned. If Value is not equal to CompareValue,
|
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then Value is returned. The compare exchange operation must be performed using
|
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MP safe mechanisms.
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@param Value A pointer to the 32-bit value for the compare exchange
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operation.
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@param CompareValue 32-bit value used in compare operation.
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@param ExchangeValue 32-bit value used in exchange operation.
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@return The original *Value before exchange.
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**/
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UINT32
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EFIAPI
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InternalSyncCompareExchange32 (
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IN OUT volatile UINT32 *Value,
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IN UINT32 CompareValue,
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IN UINT32 ExchangeValue
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)
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{
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__asm__ __volatile__ (
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"lock \n\t"
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2018-09-29 20:18:34 +02:00
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"cmpxchgl %3, %1 \n\t"
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: "=a" (CompareValue), // %0
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"=m" (*Value) // %1
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: "a" (CompareValue), // %2
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"r" (ExchangeValue), // %3
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"m" (*Value) // %4
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2010-05-18 07:37:58 +02:00
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: "memory",
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"cc"
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);
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2018-06-27 15:11:33 +02:00
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2010-05-19 08:06:40 +02:00
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return CompareValue;
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2010-05-18 07:37:58 +02:00
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}
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/**
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Performs an atomic compare exchange operation on a 64-bit unsigned integer.
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|
Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
|
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by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
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CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
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The compare exchange operation must be performed using MP safe mechanisms.
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@param Value A pointer to the 64-bit value for the compare exchange
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operation.
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@param CompareValue 64-bit value used in compare operation.
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@param ExchangeValue 64-bit value used in exchange operation.
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@return The original *Value before exchange.
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**/
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UINT64
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EFIAPI
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InternalSyncCompareExchange64 (
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IN OUT volatile UINT64 *Value,
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IN UINT64 CompareValue,
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IN UINT64 ExchangeValue
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)
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{
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__asm__ __volatile__ (
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"lock \n\t"
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2018-09-29 20:18:34 +02:00
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"cmpxchgq %3, %1 \n\t"
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: "=a" (CompareValue), // %0
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"=m" (*Value) // %1
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: "a" (CompareValue), // %2
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"r" (ExchangeValue), // %3
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"m" (*Value) // %4
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2010-05-18 07:37:58 +02:00
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: "memory",
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"cc"
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);
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2018-06-27 15:11:33 +02:00
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2010-05-18 07:37:58 +02:00
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return CompareValue;
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}
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