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audk/IntelFsp2Pkg/Library/BaseCacheLib/CacheLibInternal.h

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Add IntelFsp2Pkg and IntelFsp2WrapperPkg. Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
2016-05-13 07:00:53 +02:00
/** @file
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
IntelFsp2Pkg: Replace BSD License with BSD+Patent License https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2019-04-04 01:04:04 +02:00
SPDX-License-Identifier: BSD-2-Clause-Patent
Add IntelFsp2Pkg and IntelFsp2WrapperPkg. Add FSP2.0 support. This series of patch is to support FSP2.0 specification at https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf Some major updates include: 1) One FSP binary is separated to multiple components: FSP-T, FSP-M, FSP-S, and optional FSP-O. Each component has its own configuration data region. 2) All FSP-APIs use same UPD format - FSP_UPD_HEADER. 3) Add EnumInitPhaseEndOfFirmware notifyphase. 4) FSP1.1/FSP1.0 compatibility is NOT maintained. 5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg, to indicate that it is for FspWrapper only. IntelFspPkg and IntelFspWrapperPkg will be deprecated. The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg and IntelFsp2WrapperPkg. The old platform can still use IntelFspPkg and IntelFspWrapperPkg for compatibility consideration. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
2016-05-13 07:00:53 +02:00
**/
#ifndef _CACHE_LIB_INTERNAL_H_
#define _CACHE_LIB_INTERNAL_H_
#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200
#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F
#define V_EFI_FIXED_MTRR_NUMBER 11
#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250
#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258
#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259
#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268
#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269
#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF
#define B_EFI_MSR_CACHE_MTRR_VALID BIT11
#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11
#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10
#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)
#define EFI_MSR_VALID_MASK 0xFFFFFFFFF
#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000
#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000
#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000
// Leave one MTRR pairs for OS use
#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1
#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \
(EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)
#define EFI_MSR_IA32_MTRR_CAP 0x000000FE
#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12
#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11
#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10
#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
#define CPUID_EXTENDED_FUNCTION 0x80000000
#endif