mirror of https://github.com/acidanthera/audk.git
189 lines
6.4 KiB
ArmAsm
189 lines
6.4 KiB
ArmAsm
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#
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# Copyright (c) 2011, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http:#opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#
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#include <AsmMacroIoLib.h>
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#include <Library/PcdLib.h>
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#include <AutoGen.h>
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#include <AsmMacroIoLib.h>
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#Start of the code section
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.text
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#Maintain 8 byte alignment
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.align 3
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#Export Initialize SMC symbol
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GCC_ASM_EXPORT(InitializeSMC)
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# Static memory configuation definitions for SMC
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.set SmcDirectCmd, 0x10
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.set SmcSetCycles, 0x14
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.set SmcSetOpMode, 0x18
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# CS0 CS0-Interf0 NOR1 flash on the motherboard
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# CS1 CS1-Interf0 Reserved for the motherboard
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# CS2 CS2-Interf0 SRAM on the motherboard
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# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard
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# CS4 CS0-Interf1 NOR2 flash on the motherboard
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# CS5 CS1-Interf1 memory-mapped peripherals
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# CS6 CS2-Interf1 memory-mapped peripherals
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# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.
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# IN r1 SmcBase
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# IN r2 VideoSRamBase
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# NOTE: This code is been called before any stack has been setup. It means some registers
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# could be overwritten (case of 'r0')
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ASM_PFX(InitializeSMC):
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#
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# Setup NOR1 (CS0-Interface0)
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#
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#Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
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#Read cycle timeout = 0xA (0:3)
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#Write cycle timeout = 0x3(7:4)
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#OE Assertion Delay = 0x9(11:8)
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#WE Assertion delay = 0x3(15:12)
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#Page cycle timeout = 0x2(19:16)
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LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
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str r0, [r1, #SmcSetCycles]
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#Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000028 = ReadMemoryBurstLength:continuous
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# 0x00000280 = WriteMemoryBurstLength:continuous
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# 0x00000800 = Set Address Valid
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LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
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str r0, [r1, #SmcSetOpMode]
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#Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
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# 0x00000000 = ChipSelect0-Interface 0
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000
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str r0, [r1, #SmcDirectCmd]
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#
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# Setup SRAM (CS2-Interface0)
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#
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LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158
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str r0, [r1, #SmcSetCycles]
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000800 = Set Address Valid
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LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802
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str r0, [r1, #SmcSetOpMode]
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# 0x01000000 = ChipSelect2-Interface 0
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000
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str r0, [r1, #SmcDirectCmd]
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#
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# USB/Eth/VRAM (CS3-Interface0)
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#
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LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA
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str r0, [r1, #SmcSetCycles]
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000004 = Memory reads are synchronous
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# 0x00000040 = Memory writes are synchronous
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LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
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str r0, [r1, #SmcSetOpMode]
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# 0x01800000 = ChipSelect3-Interface 0
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000
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str r0, [r1, #SmcDirectCmd]
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#
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# Setup NOR3 (CS0-Interface1)
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#
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LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A
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str r0, [r1, #SmcSetCycles]
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000028 = ReadMemoryBurstLength:continuous
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# 0x00000280 = WriteMemoryBurstLength:continuous
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# 0x00000800 = Set Address Valid
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LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA
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str r0, [r1, #SmcSetOpMode]
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# 0x02000000 = ChipSelect0-Interface 1
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000
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str r0, [r1, #SmcDirectCmd]
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#
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# Setup Peripherals (CS3-Interface1)
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#
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LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156
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str r0, [r1, #SmcSetCycles]
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000004 = Memory reads are synchronous
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# 0x00000040 = Memory writes are synchronous
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LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
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str r0, [r1, #SmcSetOpMode]
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# 0x03800000 = ChipSelect3-Interface 1
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000
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str r0, [r1, #SmcDirectCmd]
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#
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# Setup VRAM (CS1-Interface0)
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#
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LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249
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str r0, [r1, #SmcSetCycles]
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# 0x00000002 = MemoryWidth: 32bit
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# 0x00000004 = Memory reads are synchronous
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# 0x00000040 = Memory writes are synchronous
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LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046
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str r0, [r1, #SmcSetOpMode]
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# 0x00800000 = ChipSelect1-Interface 0
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# 0x00400000 = CmdTypes: UpdateRegs
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LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000
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str r0, [r1, #SmcDirectCmd]
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#
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# Page mode setup for VRAM
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#
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#read current state
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
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str r0, [r2, #0]
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ldr r0, [r2, #0]
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#enable page mode
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
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str r0, [r2, #0]
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LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090
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str r0, [r2, #0]
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#confirm page mode enabled
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ldr r0, [r2, #0]
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ldr r0, [r2, #0]
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LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000
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str r0, [r2, #0]
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ldr r0, [r2, #0]
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bx lr
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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