mirror of https://github.com/acidanthera/audk.git
329 lines
10 KiB
C
329 lines
10 KiB
C
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/** @file NorFlashDxe.h
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Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __NOR_FLASH_DXE_H__
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#define __NOR_FLASH_DXE_H__
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#include <Base.h>
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#include <PiDxe.h>
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#include <Protocol/BlockIo.h>
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#include <Protocol/FirmwareVolumeBlock.h>
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#include <ArmPlatform.h>
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#define HIGH_16_BITS 0xFFFF0000
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#define LOW_16_BITS 0x0000FFFF
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#define LOW_8_BITS 0x000000FF
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// Hardware addresses
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#define VE_SYSTEM_REGISTERS_OFFSET 0x00000000
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#define SYSTEM_REGISTER_SYS_FLASH 0x0000004C
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#define VE_REGISTER_SYS_FLASH_ADDR ( ARM_VE_BOARD_PERIPH_BASE + VE_SYSTEM_REGISTERS_OFFSET + SYSTEM_REGISTER_SYS_FLASH )
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// Device access macros
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// These are necessary because we use 2 x 16bit parts to make up 32bit data
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#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
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#define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
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#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
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// Each command must be sent simultaneously to both chips,
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// i.e. at the lower 16 bits AND at the higher 16 bits
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#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ( (volatile UINTN *)((BaseAddr) + ((OffsetAddr) << 2)) )
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#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
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#define SEND_NOR_COMMAND(BaseAddr,OffsetAddr,Cmd) ( *CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) = CREATE_DUAL_CMD(Cmd) )
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#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)(Lba * LbaSize) )
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// Status Register Bits
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#define P30_SR_BIT_WRITE 0x00800080 /* Bit 7 */
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#define P30_SR_BIT_ERASE_SUSPEND 0x00400040 /* Bit 6 */
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#define P30_SR_BIT_ERASE 0x00200020 /* Bit 5 */
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#define P30_SR_BIT_PROGRAM 0x00100010 /* Bit 4 */
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#define P30_SR_BIT_VPP 0x00080008 /* Bit 3 */
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#define P30_SR_BIT_PROGRAM_SUSPEND 0x00040004 /* Bit 2 */
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#define P30_SR_BIT_BLOCK_LOCKED 0x00020002 /* Bit 1 */
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#define P30_SR_BIT_BEFP 0x00010001 /* Bit 0 */
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// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
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// On chip buffer size for buffered programming operations
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// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
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// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
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#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
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#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
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#define MAX_BUFFERED_PROG_ITERATIONS 10000000
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#define BOUNDARY_OF_32_WORDS 0x7F
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// CFI Addresses
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#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
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#define P30_CFI_ADDR_VENDOR_ID 0x13
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// CFI Data
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#define CFI_QRY 0x00595251
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// READ Commands
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#define P30_CMD_READ_DEVICE_ID 0x0090
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#define P30_CMD_READ_STATUS_REGISTER 0x0070
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#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
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#define P30_CMD_READ_ARRAY 0x00FF
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#define P30_CMD_READ_CFI_QUERY 0x0098
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// WRITE Commands
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#define P30_CMD_WORD_PROGRAM_SETUP 0x0040
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#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
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#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
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#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
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#define P30_CMD_BEFP_SETUP 0x0080
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#define P30_CMD_BEFP_CONFIRM 0x00D0
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// ERASE Commands
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#define P30_CMD_BLOCK_ERASE_SETUP 0x0020
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#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
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// SUSPEND Commands
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#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
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#define P30_CMD_SUSPEND_RESUME 0x00D0
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// BLOCK LOCKING / UNLOCKING Commands
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#define P30_CMD_LOCK_BLOCK_SETUP 0x0060
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#define P30_CMD_LOCK_BLOCK 0x0001
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#define P30_CMD_UNLOCK_BLOCK 0x00D0
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#define P30_CMD_LOCK_DOWN_BLOCK 0x002F
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// PROTECTION Commands
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#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
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// CONFIGURATION Commands
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#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
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#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
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#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
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#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
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#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
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typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
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typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
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typedef struct {
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UINTN BaseAddress;
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UINTN Size;
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UINTN BlockSize;
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BOOLEAN SupportFvb;
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EFI_GUID Guid;
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} NOR_FLASH_DESCRIPTION;
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typedef struct {
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VENDOR_DEVICE_PATH Vendor;
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EFI_DEVICE_PATH_PROTOCOL End;
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} NOR_FLASH_DEVICE_PATH;
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struct _NOR_FLASH_INSTANCE {
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UINT32 Signature;
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EFI_HANDLE Handle;
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BOOLEAN Initialized;
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NOR_FLASH_INITIALIZE Initialize;
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UINTN BaseAddress;
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UINTN Size;
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EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
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EFI_BLOCK_IO_MEDIA Media;
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BOOLEAN SupportFvb;
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EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
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NOR_FLASH_DEVICE_PATH DevicePath;
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};
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EFI_STATUS
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EFIAPI
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NorFlashBlkIoInitialize (
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IN NOR_FLASH_INSTANCE* Instance
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);
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EFI_STATUS
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NorFlashReadCfiData (
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IN UINTN BaseAddress,
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IN UINTN CFI_Offset,
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IN UINT32 NumberOfBytes,
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OUT UINT32 *Data
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);
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EFI_STATUS
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NorFlashWriteBuffer (
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IN UINTN TargetAddress,
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IN UINTN BufferSizeInBytes,
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IN UINT32 *Buffer
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);
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//
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// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
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//
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EFI_STATUS
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EFIAPI
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NorFlashBlockIoReset (
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IN EFI_BLOCK_IO_PROTOCOL *This,
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IN BOOLEAN ExtendedVerification
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);
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//
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// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
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//
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EFI_STATUS
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EFIAPI
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NorFlashBlockIoReadBlocks (
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IN EFI_BLOCK_IO_PROTOCOL *This,
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IN UINT32 MediaId,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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OUT VOID *Buffer
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);
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//
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// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
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//
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EFI_STATUS
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EFIAPI
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NorFlashBlockIoWriteBlocks (
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IN EFI_BLOCK_IO_PROTOCOL *This,
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IN UINT32 MediaId,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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IN VOID *Buffer
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);
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//
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// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
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//
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EFI_STATUS
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EFIAPI
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NorFlashBlockIoFlushBlocks (
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IN EFI_BLOCK_IO_PROTOCOL *This
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);
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//
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// NorFlashFvbDxe.c
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//
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EFI_STATUS
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EFIAPI
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NorFlashFvbInitialize (
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IN NOR_FLASH_INSTANCE* Instance
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);
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EFI_STATUS
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EFIAPI
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FvbGetAttributes(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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OUT EFI_FVB_ATTRIBUTES_2 *Attributes
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);
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EFI_STATUS
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EFIAPI
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FvbSetAttributes(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
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);
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EFI_STATUS
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EFIAPI
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FvbGetPhysicalAddress(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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OUT EFI_PHYSICAL_ADDRESS *Address
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);
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EFI_STATUS
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EFIAPI
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FvbGetBlockSize(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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OUT UINTN *BlockSize,
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OUT UINTN *NumberOfBlocks
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);
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EFI_STATUS
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EFIAPI
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FvbRead(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN OUT UINT8 *Buffer
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);
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EFI_STATUS
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EFIAPI
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FvbWrite(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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IN EFI_LBA Lba,
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IN UINTN Offset,
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IN OUT UINTN *NumBytes,
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IN UINT8 *Buffer
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);
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EFI_STATUS
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EFIAPI
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FvbEraseBlocks(
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IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
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...
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);
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//
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// NorFlashDxe.c
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//
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EFI_STATUS
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NorFlashUnlockAndEraseSingleBlock(
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IN UINTN BlockAddress
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);
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EFI_STATUS
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NorFlashWriteSingleBlock (
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IN UINTN DeviceBaseAddress,
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IN EFI_LBA Lba,
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IN UINT32 *pDataBuffer,
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IN UINT32 BlockSizeInWords
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);
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EFI_STATUS
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NorFlashWriteBlocks (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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IN VOID *Buffer
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);
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EFI_STATUS
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NorFlashReadBlocks (
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IN NOR_FLASH_INSTANCE *Instance,
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IN EFI_LBA Lba,
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IN UINTN BufferSizeInBytes,
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OUT VOID *Buffer
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);
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EFI_STATUS
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NorFlashReset (
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IN NOR_FLASH_INSTANCE *Instance
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);
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#endif /* __NOR_FLASH_DXE_H__ */
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