2010-05-08 21:32:03 +02:00
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/** @file
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OMAP35xx DMA abstractions modeled on PCI IO protocol. EnableDma()/DisableDma()
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are from OMAP35xx TRM.
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Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <Base.h>
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#include <Library/DebugLib.h>
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#include <Library/OmapDmaLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UncachedMemoryAllocationLib.h>
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#include <Library/IoLib.h>
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#include <Omap3530/Omap3530.h>
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#include <Protocol/Cpu.h>
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typedef struct {
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EFI_PHYSICAL_ADDRESS HostAddress;
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EFI_PHYSICAL_ADDRESS DeviceAddress;
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UINTN NumberOfBytes;
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DMA_MAP_OPERATION Operation;
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} MAP_INFO_INSTANCE;
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EFI_CPU_ARCH_PROTOCOL *gCpu;
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/**
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Configure OMAP DMA Channel
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@param Channel DMA Channel to configure
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@param Dma4 Pointer to structure used to initialize DMA registers for the Channel
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@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
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@retval EFI_INVALID_PARAMETER Channel is not valid
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@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
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**/
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EFI_STATUS
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EFIAPI
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EnableDmaChannel (
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IN UINTN Channel,
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IN OMAP_DMA4 *DMA4
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)
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{
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UINT32 RegVal;
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if (Channel > DMA4_MAX_CHANNEL) {
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return EFI_INVALID_PARAMETER;
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}
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/* 1) Configure the transfer parameters in the logical DMA registers */
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/*-------------------------------------------------------------------*/
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/* a) Set the data type CSDP[1:0], the Read/Write Port access type
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CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
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write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
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// Read CSDP
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RegVal = MmioRead32 (DMA4_CSDP (Channel));
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// Build reg
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RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
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RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
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RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
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RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
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RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
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RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
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RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
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RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
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// Write CSDP
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MmioWrite32 (DMA4_CSDP (Channel), RegVal);
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/* b) Set the number of element per frame CEN[23:0]*/
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MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
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/* c) Set the number of frame per block CFN[15:0]*/
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MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
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/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
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MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
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MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
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/* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
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read/write priority CCR[6]/CCR[26]
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I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
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LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
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*/
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// Read CCR
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RegVal = MmioRead32 (DMA4_CCR (Channel));
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// Build reg
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RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber);
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RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
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RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));
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RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));
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RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6));
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RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));
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// Write CCR
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MmioWrite32 (DMA4_CCR (Channel), RegVal);
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/* f)- Set the source element index CSEI[15:0]*/
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MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
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/* - Set the source frame index CSFI[15:0]*/
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MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
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/* - Set the destination element index CDEI[15:0]*/
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MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
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/* - Set the destination frame index CDFI[31:0]*/
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MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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2010-05-11 02:06:47 +02:00
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MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
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// Enable all the status bits since we are polling
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MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL);
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MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
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2010-05-08 21:32:03 +02:00
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/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
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/*--------------------------------------------------------------*/
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//write enable bit
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2010-05-11 02:06:47 +02:00
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MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer
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2010-05-08 21:32:03 +02:00
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return EFI_SUCCESS;
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}
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/**
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Turn of DMA channel configured by EnableDma().
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@param Channel DMA Channel to configure
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2010-05-11 02:06:47 +02:00
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@param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
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@param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
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2010-05-08 21:32:03 +02:00
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@retval EFI_SUCCESS DMA hardware disabled
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@retval EFI_INVALID_PARAMETER Channel is not valid
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@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
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**/
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EFI_STATUS
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EFIAPI
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DisableDmaChannel (
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2010-05-11 02:06:47 +02:00
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IN UINTN Channel,
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IN UINT32 SuccessMask,
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IN UINT32 ErrorMask
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2010-05-08 21:32:03 +02:00
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)
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{
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2010-05-11 02:06:47 +02:00
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EFI_STATUS Status = EFI_SUCCESS;
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UINT32 Reg;
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2010-05-08 21:32:03 +02:00
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if (Channel > DMA4_MAX_CHANNEL) {
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return EFI_INVALID_PARAMETER;
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}
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2010-05-11 02:06:47 +02:00
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do {
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Reg = MmioRead32 (DMA4_CSR(Channel));
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if ((Reg & ErrorMask) != 0) {
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Status = EFI_DEVICE_ERROR;
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DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg));
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break;
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}
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} while ((Reg & SuccessMask) != SuccessMask);
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// Disable all status bits and clear them
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MmioWrite32 (DMA4_CICR (Channel), 0);
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MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET);
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2010-05-08 21:32:03 +02:00
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MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
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2010-05-11 02:06:47 +02:00
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return Status;
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2010-05-08 21:32:03 +02:00
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}
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2010-05-11 02:06:47 +02:00
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2010-05-08 21:32:03 +02:00
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/**
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Provides the DMA controller-specific addresses needed to access system memory.
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Operation is relative to the DMA bus master.
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@param Operation Indicates if the bus master is going to read or write to system memory.
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@param HostAddress The system memory address to map to the DMA controller.
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@param NumberOfBytes On input the number of bytes to map. On output the number of bytes
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that were mapped.
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@param DeviceAddress The resulting map address for the bus master controller to use to
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access the hosts HostAddress.
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@param Mapping A resulting value to pass to Unmap().
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@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
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@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
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**/
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EFI_STATUS
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EFIAPI
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DmaMap (
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IN DMA_MAP_OPERATION Operation,
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IN VOID *HostAddress,
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IN OUT UINTN *NumberOfBytes,
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OUT PHYSICAL_ADDRESS *DeviceAddress,
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OUT VOID **Mapping
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)
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{
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MAP_INFO_INSTANCE *Map;
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if ( HostAddress == NULL || NumberOfBytes == NULL ||
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DeviceAddress == NULL || Mapping == NULL ) {
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return EFI_INVALID_PARAMETER;
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}
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if (Operation >= MapOperationMaximum) {
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return EFI_INVALID_PARAMETER;
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}
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*DeviceAddress = ConvertToPhysicalAddress (HostAddress);
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// Remember range so we can flush on the other side
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Map = AllocatePool (sizeof (MAP_INFO_INSTANCE));
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if (Map == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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*Mapping = Map;
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Map->HostAddress = (UINTN)HostAddress;
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Map->DeviceAddress = *DeviceAddress;
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Map->NumberOfBytes = *NumberOfBytes;
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Map->Operation = Operation;
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// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
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gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
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return EFI_SUCCESS;
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}
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/**
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Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
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operation and releases any corresponding resources.
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@param Mapping The mapping value returned from DmaMap*().
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@retval EFI_SUCCESS The range was unmapped.
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@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
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**/
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EFI_STATUS
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EFIAPI
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DmaUnmap (
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IN VOID *Mapping
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)
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{
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MAP_INFO_INSTANCE *Map;
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if (Mapping == NULL) {
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ASSERT (FALSE);
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return EFI_INVALID_PARAMETER;
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}
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Map = (MAP_INFO_INSTANCE *)Mapping;
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if (Map->Operation == MapOperationBusMasterWrite) {
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//
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// Make sure we read buffer from uncached memory and not the cache
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//
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gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
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}
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FreePool (Map);
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return EFI_SUCCESS;
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}
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/**
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Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
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mapping.
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@param MemoryType The type of memory to allocate, EfiBootServicesData or
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EfiRuntimeServicesData.
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@param Pages The number of pages to allocate.
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@param HostAddress A pointer to store the base system memory address of the
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allocated range.
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@retval EFI_SUCCESS The requested memory pages were allocated.
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@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
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MEMORY_WRITE_COMBINE and MEMORY_CACHED.
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@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
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@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
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**/EFI_STATUS
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EFIAPI
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DmaAllocateBuffer (
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IN EFI_MEMORY_TYPE MemoryType,
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IN UINTN Pages,
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OUT VOID **HostAddress
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)
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{
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if (HostAddress == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
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//
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// We used uncached memory to keep coherency
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//
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if (MemoryType == EfiBootServicesData) {
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*HostAddress = UncachedAllocatePages (Pages);
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} else if (MemoryType != EfiRuntimeServicesData) {
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*HostAddress = UncachedAllocateRuntimePages (Pages);
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} else {
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return EFI_INVALID_PARAMETER;
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}
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return EFI_SUCCESS;
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}
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/**
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Frees memory that was allocated with DmaAllocateBuffer().
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@param Pages The number of pages to free.
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@param HostAddress The base system memory address of the allocated range.
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@retval EFI_SUCCESS The requested memory pages were freed.
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@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
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was not allocated with DmaAllocateBuffer().
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**/
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EFI_STATUS
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EFIAPI
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DmaFreeBuffer (
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IN UINTN Pages,
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IN VOID *HostAddress
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)
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{
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if (HostAddress == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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UncachedFreePages (HostAddress, Pages);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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EFIAPI
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OmapDmaLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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// Get the Cpu protocol for later use
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Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
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ASSERT_EFI_ERROR(Status);
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return EFI_SUCCESS;
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}
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