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audk/BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc

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ARM Packages: CRLF fixup Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 16:30:34 +01:00
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
ARM Packages: Removed trailing spaces Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 15:29:52 +02:00
//
BeagleBoardPkg: Replace BSD License with BSD+Patent License https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2019-04-04 01:03:25 +02:00
// SPDX-License-Identifier: BSD-2-Clause-Patent
ARM Packages: CRLF fixup Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12 16:30:34 +01:00
//
error = continue
unload
error = abort
setreg @CP15_CONTROL = 0x0005107E
setreg @cpsr=0x000000D3
; General clock settings.
setmem /32 0x48307270=0x00000080
setmem /32 0x48306D40=0x00000003
setmem /32 0x48005140=0x03020A50
;Clock configuration
setmem /32 0x48004A40=0x0000030A
setmem /32 0x48004C40=0x00000015
;DPLL3 (Core) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D40=0x094C0C00
;DPLL4 (Peripheral) settings
setmem /32 0x48004D00=0x00370037
setmem /32 0x48004D30=0x00000000
setmem /32 0x48004D44=0x0001B00C
setmem /32 0x48004D48=0x00000009
;DPLL1 (MPU) settings
setmem /32 0x48004904=0x00000037
setmem /32 0x48004934=0x00000000
setmem /32 0x48004940=0x0011F40C
setmem /32 0x48004944=0x00000001
setmem /32 0x48004948=0x00000000
;RAM setup.
setmem /16 0x6D000010=0x0000
setmem /16 0x6D000040=0x0001
setmem /16 0x6D000044=0x0100
setmem /16 0x6D000048=0x0000
setmem /32 0x6D000060=0x0000000A
setmem /32 0x6D000070=0x00000081
setmem /16 0x6D000040=0x0003
setmem /32 0x6D000080=0x02D04011
setmem /16 0x6D000084=0x0032
setmem /16 0x6D00008C=0x0000
setmem /32 0x6D00009C=0xBA9DC4C6
setmem /32 0x6D0000A0=0x00012522
setmem /32 0x6D0000A4=0x0004E201
setmem /16 0x6D000040=0x0003
setmem /32 0x6D0000B0=0x02D04011
setmem /16 0x6D0000B4=0x0032
setmem /16 0x6D0000BC=0x0000
setmem /32 0x6D0000C4=0xBA9DC4C6
setmem /32 0x6D0000C8=0x00012522
ARM Packages: Corrected non-DOS line endings Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19 15:22:20 +02:00
setmem /32 0x6D0000D4=0x0004E201