mirror of https://github.com/acidanthera/audk.git
525 lines
21 KiB
C
525 lines
21 KiB
C
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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\section I2cDriverStack I2C Driver Stack
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The following is a representation of the I<sup>2</sup>C (I2C)
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driver stack and an I2C bus layout.
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<code><pre>
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+-----------------+
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| Application |
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+-----------------+
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| Third Party or UEFI
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V
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+--------+ +-----------------+
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| Slave | | Third Party |
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| Driver | | I2C Device |
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| | | Driver |
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+--------+ +-----------------+
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| BUS |
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| V
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| +-----------------+
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| | I2C Bus Driver |------------------.
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| +-----------------+ |
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| | |
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| HOST | BUS |
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| | CONFIGURATION |
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SLAVE | V MANAGEMENT | ACPI
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| +-----------------+ |
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| | I2C Host Driver |----------. |
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| +-----------------+ | |
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| | | |
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| MASTER | V V
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| | +-------=-------------+
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| V | I2C Platform Driver |
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| +-----------------+ +---------------------+
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`------>| I2C Port Driver | | |
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+-----------------+ | |
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Software | | |
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--------------------------------------------------
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Hardware | | |
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V | |
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+-----------------+ | |
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| I2C Controller | | |
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+-----------------+ | |
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| | |
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----------------------- | |
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I2C Bus | | |
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| +------------+ | |
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+----| High speed | | |
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| | I2C device | | |
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| | 0x01 | | |
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| +------------+ | |
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| | |
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+---------+ 0 | |
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| Switch |<------------------` |
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+---------+ 1 |
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| |
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| +------------+ |
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+----| Fast speed | |
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| | I2C device | |
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| | 0x02 | |
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| +------------+ |
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| |
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+-------------+ |
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| Multiplexer |<-----------------------`
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+-------------+
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0 | | 1
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| | +-------------+
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| +----| Third Party |
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| | | I2C Device |
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| | | 0x03, 0x04 |
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| | +-------------+
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| +-------------+
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+------------| Third Party |
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| | I2C Device |
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| | 0x03, 0x04 |
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| +-------------+
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</pre></code>
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The platform hardware designer chooses the bus layout based upon
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the platform, I2C chip and software requirements. The design uses
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switches to truncate the bus to enable higher speed operation for a
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subset of devices which are placed closer to the controller. When the
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switch is on, the extended bus must operate at a lower speed. The
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design uses multiplexer to create separate address spaces enabling
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the use of multiple devices which would otherwise have conflicting
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addresses. See the
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<a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C
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Specification</a> for more details.
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N.B. Some operating systems may prohibit the changing of switches
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and multiplexers in the I2C bus. In this case the platform hardware
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and software designers must select a single I2C bus configuration
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consisting of constant input values for the switches and multiplexers.
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The platform software designer must then ensure that this I2C bus
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configuration is enabled prior to passing control to the operating
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system.
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The platform hardware designer needs to provide the platform software
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designer the following data for each I2C bus:
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1. Which controller controls this bus
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2. A list of logic blocks contained in one or more I2C devices:
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a. I2C device which contains this logic block
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b. Logic block slave address
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c. Logic block name
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3. For each configuration of the switches and multiplexer
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a. What is the maximum speed of operation
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b. What devices are accessible
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4. The settings for the switches and multiplexers when control is
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given to the operating system.
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\section ThirdPartyI2cDrivers Third Party I2C Drivers
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This layer is I2C chip specific but platform and host controller
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independent.
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Third party I2C driver writers, typically silicon vendors, need
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to provide:
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1. The device path node data that is used to select their
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driver.
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2. The order for the blocks of logic that get referenced
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by the entries in the slave address array.
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3. The hardware version of the I2C device, this value is passed
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to the third party I2C driver to enable it to perform work
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arounds for the specific hardware version. This value should
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match the value in the ACPI _HRV tag.
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The third party I2C driver uses relative addressing to abstract
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the platform specific details of the I2C device. Using an
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example I2C device containing an accelerometer and a magnetometer
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which consumes two slave addresses, one for each logic block. The
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third party I2C driver writer may choose to write two drivers, one
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for each block of logic, in which case each driver refers to the
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single I2C slave address using the relative value of zero (0).
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However if the third party I2C driver writer chooses to write a
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single driver which consumes multiple slave addresses then the
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third party I2C driver writer needs to convey the order of the
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I2C slave address entries in the slave address array to the
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platform software designer. For the example:
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0: Accelerometer
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1: Magnetometer
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The platform hardware designer picks the actual slave addresses
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from the I2C device's data sheet and provides this information
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to the platform software designer. The platform software designer
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then places the slave addresses into the slave address array in the
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order specified by the third party I2C driver writer. The third
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party driver I2C writer then indirectly references this array by
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specifying the index value as the relative slave address. The
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relative value always starts at zero (0) and its maximum value is
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the number of entries in slave address array minus one.
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The slave address is specified as a 32-bit integer to allow room
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for future slave address expansion. Only the port driver knows
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the maximum slave address value. All other drivers and
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applications must look for the EFI_NOT_FOUND status for the
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indication that the maximum slave address was exceeded.
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\section I2cBusDriver I2C Bus Driver
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This layer is platform, host controller, and I2C chip independent.
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The I2C bus driver creates a handle for each of the I2C devices
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described within the platform driver. The I2C controller's device
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path is extended with the device path node provided by the platform
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driver and attached to the handle. The third party I2C device driver
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uses the device path to determine if it may connect. For ACPI nodes,
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the third party I2C driver should use the CID or CidString value.
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The I2C bus driver validates the relative address for the I2C device
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and then converts the relative value to an actual I2C slave address.
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The request is then passed to the I2C host driver.
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\section I2cHostDriver I2C Host Driver
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This layer is platform, host controller, and I2C chip independent.
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N.B. For proper operation of the I2C bus, only the I2C bus driver
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and the I2C test application should connect to the I2C host driver
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via the EFI_I2C_HOST_DRIVER_PROTOCOL.
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The I2C host driver may access any device on the I2C bus. The I2C
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host driver has the following responsibilities:
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1. Limits the number of requests to the I2C port driver to one.
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The I2C host driver holds on to additional requests until the
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I2C port driver is available to process the request. The I2C
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requests are issued in FIFO order to the I2C port driver.
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2. Enable the proper I2C bus configuration before starting the
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I2C request on the I2C port driver
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I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress.
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I2C bus configuration zero (0) is the portion of the I2C bus that
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connects to the host controller. The bus configuration specifies
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the control values for the switches and multiplexers in the I2C bus.
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After the switches and multiplexers are properly configured, the I2C
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controller uses the slave address to access the requested I2C device.
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Since the I2C driver stack supports asynchronous operations this
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layer maintains a queue of I2C requests until the I2C controller
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is available them. When a request reaches the head of the queue
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the necessary bus configuration is enabled and then the request
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is sent to the I2C port driver.
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\section I2cPortDriver I2C Port Driver
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This layer is I2C controller specific but platform independent.
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This layer manipulates the I2C controller to perform an operation
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on the I2C bus. This layer does not configure the I2C bus so it
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is up to the caller to ensure that the I2C bus is in the proper
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configuration before issuing the I2C request.
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This layer typically needs the following information:
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1. Host controller address
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2. Controller's input clock frequency
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Depending upon the I2C controller, more data may be necessary.
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This layer may use any method to get these values: hard coded
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values, PCD values, or may choose to communicate with the platform
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layer using an undefined mechanism to get these values.
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If the I2C port driver requires data from the platform driver then
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the I2C port driver writer needs to provide the platform interface
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details to the platform software designer.
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\section I2cPlatformDriver I2C Platform Driver
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When enabling access to I2C devices within UEFI, this driver
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installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device
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descriptions to the I2C bus driver using the EFI_I2C_DEVICE
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structure. These descriptions include the bus configuration
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number required for the I2C device, the slave address array
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and the device path.
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The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional.
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This protocol needs to be specified under the following conditions:
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1. The I2C bus must operate at a frequency greater than 100 KHz
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2. The I2C bus contains switches or multiplexers.
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The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the
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I2C host driver to call into the I2C platform driver to enable
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a specific I2C bus configuration and set its maximum clock speed.
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The platform software designer collects the data requirements
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from third party I2C driver writers, the I2C controller
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driver writer, the EFI_I2C_ACPI_PROTOCOL and
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EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform
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software designer gets the necessary data from the platform
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hardware designer. The platform software designer then builds
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the data structures and implements the necessary routines to
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construct the I2C platform driver.
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\section I2cSwitches Switches and Multiplexers
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There are some I2C switches and I2C multiplexers where the control
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is done via I2C commands. When the control inputs come via the
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same I2C bus that is being configured then the platform driver must
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use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform
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driver. While the I2C host driver makes the call to the I2C
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platform driver to configure the bus, the host driver keeps the
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I2C port driver idle, to allow the I2C platform driver preform
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the necessary configuration operations.
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If however the configuration control is done via and I2C device
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connected to a different I2C bus (host controller), then it is
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possible for the platform software designer may choose between
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the following:
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1. Call into a third party I2C driver to manipulate the I2C
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bus control device.
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2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C
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driver exists for the I2C bus control device
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3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does
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not expose the I2C bus control device.
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**/
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#ifndef __I2C_MASTER_H__
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#define __I2C_MASTER_H__
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/**
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Declare the forward references
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**/
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typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL; ///< I2C master protocol
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///
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/// I2C device operation
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///
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/// This structure provides the information necessary for an operation
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/// on an I2C device
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///
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typedef struct {
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///
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/// Number of bytes to send to the I2C device
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///
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UINT32 WriteBytes;
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///
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/// Number of bytes to read, set to zero for write only operations
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///
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UINT32 ReadBytes;
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///
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/// Address of the buffer containing the data to send to the I2C device.
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/// The WriteBuffer must be at least WriteBytes in length.
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///
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UINT8 *WriteBuffer;
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///
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/// Address of the buffer to receive data from the I2C device. Use NULL
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/// for write only operations. The ReadBuffer must be at least ReadBytes
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/// in length.
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///
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UINT8 *ReadBuffer;
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///
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/// Timeout for the I2C operation in 100 ns units
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///
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UINT32 Timeout;
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} EFI_I2C_REQUEST_PACKET;
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/**
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Set the I2C controller bus clock frequency.
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This routine must be called at or below TPL_NOTIFY.
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The software and controller do a best case effort of using the specified
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frequency for the I2C bus. If the frequency does not match exactly then
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the controller will use a slightly lower frequency to avoid
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exceeding the operating conditions for any of the I2C devices on the bus.
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For example if 400 KHz was specified and the controller's divide network
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only supports 402 KHz or 398 KHz then the controller would be set to 398
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KHz. However if the desired frequency is 400 KHz and the controller only
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supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.
|
||
|
|
|
||
|
|
@param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
|
||
|
|
structure
|
||
|
|
@param[in] BusClockHertz New I2C bus clock frequency in Hertz
|
||
|
|
|
||
|
|
@retval EFI_SUCCESS The bus frequency was set successfully.
|
||
|
|
@retval EFI_UNSUPPORTED The controller does not support this frequency.
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
EFI_STATUS
|
||
|
|
(EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) (
|
||
|
|
IN CONST EFI_I2C_MASTER_PROTOCOL *This,
|
||
|
|
IN UINTN BusClockHertz
|
||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Reset the I2C controller and configure it for use
|
||
|
|
|
||
|
|
This routine must be called at or below TPL_NOTIFY.
|
||
|
|
|
||
|
|
The I2C controller is reset and the I2C bus frequency is set to 100 KHz.
|
||
|
|
|
||
|
|
@param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
|
||
|
|
structure
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
VOID
|
||
|
|
(EFIAPI *EFI_I2C_MASTER_RESET) (
|
||
|
|
IN CONST EFI_I2C_MASTER_PROTOCOL *This
|
||
|
|
);
|
||
|
|
|
||
|
|
/**
|
||
|
|
Start an I2C operation on the host controller
|
||
|
|
|
||
|
|
This routine must be called at or below TPL_NOTIFY. For synchronous
|
||
|
|
requests this routine must be called at or below TPL_CALLBACK.
|
||
|
|
|
||
|
|
This function initiates an I2C operation on the controller.
|
||
|
|
|
||
|
|
The operation is performed by selecting the I2C device with its slave
|
||
|
|
address and then sending all write data to the I2C device. If read data
|
||
|
|
is requested, a restart is sent followed by the slave address and then
|
||
|
|
the read data is clocked into the I2C controller and placed in the read
|
||
|
|
buffer. When the operation completes, the status value is returned and
|
||
|
|
then the event is set.
|
||
|
|
|
||
|
|
N.B. The typical consumer of this API is the I2C host driver.
|
||
|
|
Extreme care must be taken by other consumers of this API to
|
||
|
|
prevent confusing the third party I2C drivers due to a state
|
||
|
|
change at the I2C device which the third party I2C drivers did
|
||
|
|
not initiate. I2C platform drivers may use this API within
|
||
|
|
these guidelines.
|
||
|
|
|
||
|
|
N.B. This API supports only one operation, no queuing support
|
||
|
|
exists at this layer. This API assumes that the I2C bus is in
|
||
|
|
the correct configuration for the I2C request.
|
||
|
|
|
||
|
|
@param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
|
||
|
|
structure
|
||
|
|
@param[in] SlaveAddress Address of the device on the I2C bus.
|
||
|
|
@param[in] Event Event to set for asynchronous operations,
|
||
|
|
NULL for synchronous operations
|
||
|
|
@param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
|
||
|
|
structure describing the I2C operation
|
||
|
|
@param[out] I2cStatus Optional buffer to receive the I2C operation
|
||
|
|
completion status
|
||
|
|
|
||
|
|
@retval EFI_SUCCESS The operation completed successfully.
|
||
|
|
@retval EFI_ABORTED The request did not complete because the driver
|
||
|
|
was shutdown.
|
||
|
|
@retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
|
||
|
|
@retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
|
||
|
|
This could indicate the slave device is not present.
|
||
|
|
@retval EFI_INVALID_PARAMETER RequestPacket is NULL
|
||
|
|
@retval EFI_INVALID_PARAMETER TPL is too high
|
||
|
|
@retval EFI_NOT_FOUND SlaveAddress exceeds maximum address
|
||
|
|
@retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
|
||
|
|
the event and then read status pointed to by
|
||
|
|
the request packet.
|
||
|
|
@retval EFI_NO_RESPONSE The I2C device is not responding to the
|
||
|
|
slave address. EFI_DEVICE_ERROR may also be
|
||
|
|
returned if the controller cannot distinguish
|
||
|
|
when the NACK occurred.
|
||
|
|
@retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
|
||
|
|
@retval EFI_TIMEOUT The transaction did not complete within an internally
|
||
|
|
specified timeout period.
|
||
|
|
|
||
|
|
**/
|
||
|
|
typedef
|
||
|
|
EFI_STATUS
|
||
|
|
(EFIAPI *EFI_I2C_MASTER_START_REQUEST) (
|
||
|
|
IN CONST EFI_I2C_MASTER_PROTOCOL *This,
|
||
|
|
IN UINTN SlaveAddress,
|
||
|
|
IN EFI_EVENT Event OPTIONAL,
|
||
|
|
IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
|
||
|
|
OUT EFI_STATUS *I2cStatus OPTIONAL
|
||
|
|
);
|
||
|
|
|
||
|
|
///
|
||
|
|
/// I2C master mode protocol
|
||
|
|
///
|
||
|
|
/// This protocol manipulates the I2C host controller to perform transactions as a
|
||
|
|
/// master on the I2C bus using the current state of any switches or multiplexers
|
||
|
|
/// in the I2C bus.
|
||
|
|
///
|
||
|
|
struct _EFI_I2C_MASTER_PROTOCOL {
|
||
|
|
///
|
||
|
|
/// Set the clock frequency for the I2C bus
|
||
|
|
///
|
||
|
|
EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// Reset the I2C host controller
|
||
|
|
///
|
||
|
|
EFI_I2C_MASTER_RESET Reset;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// Start an I2C transaction in master mode on the host controller
|
||
|
|
///
|
||
|
|
EFI_I2C_MASTER_START_REQUEST StartRequest;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// The maximum number of bytes the I2C host controller
|
||
|
|
/// is able to receive from the I2C bus.
|
||
|
|
///
|
||
|
|
UINT32 MaximumReceiveBytes;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// The maximum number of bytes the I2C host controller
|
||
|
|
/// is able to send on the I2C bus.
|
||
|
|
///
|
||
|
|
UINT32 MaximumTransmitBytes;
|
||
|
|
|
||
|
|
///
|
||
|
|
/// The maximum number of bytes in the I2C bus transaction.
|
||
|
|
///
|
||
|
|
UINT32 MaximumTotalBytes;
|
||
|
|
};
|
||
|
|
|
||
|
|
///
|
||
|
|
/// GUID for the EFI_I2C_MASTER_PROTOCOL
|
||
|
|
///
|
||
|
|
extern EFI_GUID gEfiI2cMasterProtocolGuid;
|
||
|
|
|
||
|
|
#endif // __I2C_MASTER_H__
|