mirror of https://github.com/acidanthera/audk.git
557 lines
14 KiB
C
557 lines
14 KiB
C
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// ++
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// TODO: fix comment to start with /*++
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//
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// Copyright (c) 2004, Intel Corporation
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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// Module Name:
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//
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// IpfDefines.h
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//
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// Abstract:
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//
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// IPF Processor Defines.
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// NOTE: This file is included by assembly files as well.
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//
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// --
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//
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#ifndef _IPFDEFINES_H
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#define _IPFDEFINES_H
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//
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// IPI DElivery Methods
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//
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#define IPI_INT_DELIVERY 0x0
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#define IPI_PMI_DELIVERY 0x2
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#define IPI_NMI_DELIVERY 0x4
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#define IPI_INIT_DELIVERY 0x5
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#define IPI_ExtINT_DELIVERY 0x7
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//
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// Define Itanium-based system registers.
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//
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// Define Itanium-based system register bit field offsets.
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//
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// Processor Status Register (PSR) Bit positions
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//
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// User / System mask
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//
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#define PSR_RV0 0
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#define PSR_BE 1
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#define PSR_UP 2
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#define PSR_AC 3
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#define PSR_MFL 4
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#define PSR_MFH 5
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//
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// PSR bits 6-12 reserved (must be zero)
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//
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#define PSR_MBZ0 6
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#define PSR_MBZ0_V 0x1ffUL L
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//
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// System only mask
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//
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#define PSR_IC 13
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#define PSR_IC_MASK (1 << 13)
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#define PSR_I 14
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#define PSR_PK 15
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#define PSR_MBZ1 16
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#define PSR_MBZ1_V 0x1UL L
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#define PSR_DT 17
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#define PSR_DFL 18
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#define PSR_DFH 19
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#define PSR_SP 20
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#define PSR_PP 21
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#define PSR_DI 22
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#define PSR_SI 23
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#define PSR_DB 24
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#define PSR_LP 25
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#define PSR_TB 26
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#define PSR_RT 27
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//
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// PSR bits 28-31 reserved (must be zero)
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//
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#define PSR_MBZ2 28
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#define PSR_MBZ2_V 0xfUL L
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//
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// Neither mask
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//
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#define PSR_CPL 32
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#define PSR_CPL_LEN 2
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#define PSR_IS 34
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#define PSR_MC 35
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#define PSR_IT 36
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#define PSR_IT_MASK 0x1000000000
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#define PSR_ID 37
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#define PSR_DA 38
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#define PSR_DD 39
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#define PSR_SS 40
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#define PSR_RI 41
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#define PSR_RI_LEN 2
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#define PSR_ED 43
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#define PSR_BN 44
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//
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// PSR bits 45-63 reserved (must be zero)
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//
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#define PSR_MBZ3 45
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#define PSR_MBZ3_V 0xfffffUL L
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//
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// Floating Point Status Register (FPSR) Bit positions
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//
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//
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// Traps
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//
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#define FPSR_VD 0
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#define FPSR_DD 1
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#define FPSR_ZD 2
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#define FPSR_OD 3
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#define FPSR_UD 4
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#define FPSR_ID 5
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//
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// Status Field 0 - Controls
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//
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#define FPSR0_FTZ0 6
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#define FPSR0_WRE0 7
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#define FPSR0_PC0 8
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#define FPSR0_RC0 10
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#define FPSR0_TD0 12
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//
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// Status Field 0 - Flags
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//
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#define FPSR0_V0 13
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#define FPSR0_D0 14
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#define FPSR0_Z0 15
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#define FPSR0_O0 16
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#define FPSR0_U0 17
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#define FPSR0_I0 18
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//
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// Status Field 1 - Controls
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//
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#define FPSR1_FTZ0 19
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#define FPSR1_WRE0 20
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#define FPSR1_PC0 21
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#define FPSR1_RC0 23
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#define FPSR1_TD0 25
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//
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// Status Field 1 - Flags
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//
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#define FPSR1_V0 26
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#define FPSR1_D0 27
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#define FPSR1_Z0 28
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#define FPSR1_O0 29
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#define FPSR1_U0 30
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#define FPSR1_I0 31
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//
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// Status Field 2 - Controls
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//
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#define FPSR2_FTZ0 32
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#define FPSR2_WRE0 33
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#define FPSR2_PC0 34
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#define FPSR2_RC0 36
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#define FPSR2_TD0 38
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//
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// Status Field 2 - Flags
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//
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#define FPSR2_V0 39
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#define FPSR2_D0 40
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#define FPSR2_Z0 41
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#define FPSR2_O0 42
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#define FPSR2_U0 43
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#define FPSR2_I0 44
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//
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// Status Field 3 - Controls
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//
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#define FPSR3_FTZ0 45
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#define FPSR3_WRE0 46
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#define FPSR3_PC0 47
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#define FPSR3_RC0 49
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#define FPSR3_TD0 51
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//
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// Status Field 0 - Flags
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//
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#define FPSR3_V0 52
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#define FPSR3_D0 53
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#define FPSR3_Z0 54
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#define FPSR3_O0 55
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#define FPSR3_U0 56
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#define FPSR3_I0 57
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//
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// FPSR bits 58-63 Reserved -- Must be zero
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//
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#define FPSR_MBZ0 58
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#define FPSR_MBZ0_V 0x3fUL L
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//
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// For setting up FPSR on kernel entry
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// All traps are disabled.
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//
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#define FPSR_FOR_KERNEL 0x3f
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#define FP_REG_SIZE 16 // 16 byte spill size
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#define HIGHFP_REGS_LENGTH (96 * 16)
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//
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// Define hardware Task Priority Register (TPR)
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//
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//
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// TPR bit positions
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//
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#define TPR_MIC 4 // Bits 0 - 3 ignored
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#define TPR_MIC_LEN 4
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#define TPR_MMI 16 // Mask Maskable Interrupt
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//
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// Define hardware Interrupt Status Register (ISR)
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//
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//
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// ISR bit positions
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//
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#define ISR_CODE 0
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#define ISR_CODE_LEN 16
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#define ISR_CODE_MASK 0xFFFF
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#define ISR_IA_VECTOR 16
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#define ISR_IA_VECTOR_LEN 8
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#define ISR_MBZ0 24
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#define ISR_MBZ0_V 0xff
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#define ISR_X 32
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#define ISR_W 33
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#define ISR_R 34
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#define ISR_NA 35
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#define ISR_SP 36
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#define ISR_RS 37
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#define ISR_IR 38
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#define ISR_NI 39
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#define ISR_MBZ1 40
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#define ISR_EI 41
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#define ISR_ED 43
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#define ISR_MBZ2 44
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#define ISR_MBZ2_V 0xfffff
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//
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// ISR codes
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//
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// For General exceptions: ISR{3:0}
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//
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#define ISR_ILLEGAL_OP 0 // Illegal operation fault
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#define ISR_PRIV_OP 1 // Privileged operation fault
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#define ISR_PRIV_REG 2 // Privileged register fauls
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#define ISR_RESVD_REG 3 // Reserved register/field flt
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#define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
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//
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// Define hardware Default Control Register (DCR)
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//
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//
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// DCR bit positions
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//
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#define DCR_PP 0
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#define DCR_BE 1
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#define DCR_LC 2
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#define DCR_MBZ0 4
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#define DCR_MBZ0_V 0xf
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#define DCR_DM 8
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#define DCR_DP 9
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#define DCR_DK 10
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#define DCR_DX 11
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#define DCR_DR 12
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#define DCR_DA 13
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#define DCR_DD 14
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#define DCR_DEFER_ALL 0x7f00
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#define DCR_MBZ1 2
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#define DCR_MBZ1_V 0xffffffffffffUL L
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//
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// Define hardware RSE Configuration Register
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//
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// RS Configuration (RSC) bit field positions
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//
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#define RSC_MODE 0
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#define RSC_PL 2
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#define RSC_BE 4
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#define RSC_MBZ0 5
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#define RSC_MBZ0_V 0x3ff
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#define RSC_LOADRS 16
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#define RSC_LOADRS_LEN 14
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#define RSC_MBZ1 30
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#define RSC_MBZ1_V 0x3ffffffffUL L
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//
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// RSC modes
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//
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#define RSC_MODE_LY (0x0) // Lazy
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#define RSC_MODE_SI (0x1) // Store intensive
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#define RSC_MODE_LI (0x2) // Load intensive
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#define RSC_MODE_EA (0x3) // Eager
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//
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// RSC Endian bit values
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//
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#define RSC_BE_LITTLE 0
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#define RSC_BE_BIG 1
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//
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// Define Interruption Function State (IFS) Register
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//
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// IFS bit field positions
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//
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#define IFS_IFM 0
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#define IFS_IFM_LEN 38
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#define IFS_MBZ0 38
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#define IFS_MBZ0_V 0x1ffffff
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#define IFS_V 63
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#define IFS_V_LEN 1
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//
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// IFS is valid when IFS_V = IFS_VALID
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//
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#define IFS_VALID 1
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//
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// Define Page Table Address (PTA)
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//
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#define PTA_VE 0
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#define PTA_VF 8
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#define PTA_SIZE 2
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#define PTA_SIZE_LEN 6
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#define PTA_BASE 15
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//
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// Define Region Register (RR)
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//
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//
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// RR bit field positions
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//
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#define RR_VE 0
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#define RR_MBZ0 1
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#define RR_PS 2
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#define RR_PS_LEN 6
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#define RR_RID 8
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#define RR_RID_LEN 24
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#define RR_MBZ1 32
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//
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// SAL uses region register 0 and RID of 1000
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//
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#define SAL_RID 0x1000
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#define SAL_RR_REG 0x0
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#define SAL_TR 0x0
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//
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// Total number of region registers
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//
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#define RR_SIZE 8
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//
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// Define Protection Key Register (PKR)
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//
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// PKR bit field positions
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//
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#define PKR_V 0
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#define PKR_WD 1
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#define PKR_RD 2
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#define PKR_XD 3
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#define PKR_MBZ0 4
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#define PKR_KEY 8
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#define PKR_KEY_LEN 24
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#define PKR_MBZ1 32
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#define PKR_VALID (1 << PKR_V)
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//
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// Number of protection key registers
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//
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#define PKRNUM 8
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//
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// Define Interruption TLB Insertion register (ITIR)
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//
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//
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// Define Translation Insertion Format (TR)
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//
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// PTE0 bit field positions
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//
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#define PTE0_P 0
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#define PTE0_MBZ0 1
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#define PTE0_MA 2
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#define PTE0_A 5
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#define PTE0_D 6
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#define PTE0_PL 7
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#define PTE0_AR 9
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#define PTE0_PPN 12
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#define PTE0_MBZ1 48
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#define PTE0_ED 52
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#define PTE0_IGN0 53
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||
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|
|
||
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|
//
|
||
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|
// ITIR bit field positions
|
||
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|
//
|
||
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|
#define ITIR_MBZ0 0
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||
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|
#define ITIR_PS 2
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||
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|
#define ITIR_PS_LEN 6
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||
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|
#define ITIR_KEY 8
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||
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|
#define ITIR_KEY_LEN 24
|
||
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|
#define ITIR_MBZ1 32
|
||
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|
#define ITIR_MBZ1_LEN 16
|
||
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|
#define ITIR_PPN 48
|
||
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|
#define ITIR_PPN_LEN 15
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||
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#define ITIR_MBZ2 63
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||
|
|
|
||
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|
#define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
|
||
|
|
#define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
|
||
|
|
// Dirty (bit 6=1), Accessed (bit 5=1),
|
||
|
|
// MA WB (bits 4-2=000), Present (bit 0=1)
|
||
|
|
//
|
||
|
|
// Memory access rights
|
||
|
|
//
|
||
|
|
#define AR_UR_KR 0x0 // user/kernel read
|
||
|
|
#define AR_URX_KRX 0x1 // user/kernel read and execute
|
||
|
|
#define AR_URW_KRW 0x2 // user/kernel read & write
|
||
|
|
#define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
|
||
|
|
#define AR_UR_KRW 0x4 // user read/kernel read,write
|
||
|
|
#define AR_URX_KRWX 0x5 // user read/execute, kernel all
|
||
|
|
#define AR_URWX_KRW 0x6 // user all, kernel read & write
|
||
|
|
#define AR_UX_KRX 0x7 // user execute only, kernel read and execute
|
||
|
|
//
|
||
|
|
// Memory attribute values
|
||
|
|
//
|
||
|
|
//
|
||
|
|
// The next 4 are all cached, non-sequential & speculative, coherent
|
||
|
|
//
|
||
|
|
#define MA_WBU 0x0 // Write back, unordered
|
||
|
|
//
|
||
|
|
// The next 3 are all non-cached, sequential & non-speculative
|
||
|
|
//
|
||
|
|
#define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
|
||
|
|
#define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
|
||
|
|
// & fetchadd exported
|
||
|
|
//
|
||
|
|
#define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
|
||
|
|
#define MA_NAT 0xf // NaT page
|
||
|
|
//
|
||
|
|
// Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
|
||
|
|
// base of IVA (Interruption Vector Address)
|
||
|
|
//
|
||
|
|
#define IVT_SIZE 0x8000
|
||
|
|
#define EXTRA_ALIGNMENT 0x1000
|
||
|
|
|
||
|
|
#define OFF_VHPTFLT 0x0000 // VHPT Translation fault
|
||
|
|
#define OFF_ITLBFLT 0x0400 // Instruction TLB fault
|
||
|
|
#define OFF_DTLBFLT 0x0800 // Data TLB fault
|
||
|
|
#define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
|
||
|
|
#define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
|
||
|
|
#define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
|
||
|
|
#define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
|
||
|
|
#define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
|
||
|
|
#define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
|
||
|
|
#define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
|
||
|
|
#define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
|
||
|
|
#define OFF_BREAKFLT 0x2C00 // Break Inst fault
|
||
|
|
#define OFF_EXTINT 0x3000 // External Interrupt
|
||
|
|
//
|
||
|
|
// Offset 0x3400 to 0x0x4C00 are reserved
|
||
|
|
//
|
||
|
|
#define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
|
||
|
|
#define OFF_KEYPERMFLT 0x5100 // Key Permission fault
|
||
|
|
#define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
|
||
|
|
#define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
|
||
|
|
#define OFF_GPFLT 0x5400 // General Exception fault
|
||
|
|
#define OFF_FPDISFLT 0x5500 // Disable-FP fault
|
||
|
|
#define OFF_NATFLT 0x5600 // NAT Consumption fault
|
||
|
|
#define OFF_SPECLNFLT 0x5700 // Speculation fault
|
||
|
|
#define OFF_DBGFLT 0x5900 // Debug fault
|
||
|
|
#define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
|
||
|
|
#define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
|
||
|
|
#define OFF_FPFLT 0x5C00 // Floating Point fault
|
||
|
|
#define OFF_FPTRAP 0x5D00 // Floating Point Trap
|
||
|
|
#define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
|
||
|
|
#define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
|
||
|
|
#define OFF_SSTEPTRAP 0x6000 // Single Step Trap
|
||
|
|
//
|
||
|
|
// Offset 0x6100 to 0x6800 are reserved
|
||
|
|
//
|
||
|
|
#define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
|
||
|
|
#define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
|
||
|
|
#define OFF_IA32INT 0x6B00 // iA32 Interrupt
|
||
|
|
#define NUMBER_OF_VECTORS 0x100
|
||
|
|
//
|
||
|
|
// Privilege levels
|
||
|
|
//
|
||
|
|
#define PL_KERNEL 0
|
||
|
|
#define PL_USER 3
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction set (IS) bits
|
||
|
|
//
|
||
|
|
#define IS_IA64 0
|
||
|
|
#define IS_IA 1
|
||
|
|
|
||
|
|
//
|
||
|
|
// RSC while in kernel: enabled, little endian, PL = 0, eager mode
|
||
|
|
//
|
||
|
|
#define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
|
||
|
|
|
||
|
|
//
|
||
|
|
// Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
|
||
|
|
//
|
||
|
|
#define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
|
||
|
|
|
||
|
|
//
|
||
|
|
// RSE disabled: disabled, PL = 0, little endian, eager mode
|
||
|
|
//
|
||
|
|
#define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
|
||
|
|
|
||
|
|
#define NAT_BITS_PER_RNAT_REG 63
|
||
|
|
|
||
|
|
//
|
||
|
|
// Macros for generating PTE0 and PTE1 value
|
||
|
|
//
|
||
|
|
#define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
|
||
|
|
( ( ed << PTE0_ED ) | \
|
||
|
|
( ppn12_47 << PTE0_PPN ) | \
|
||
|
|
( ar << PTE0_AR ) | \
|
||
|
|
( pl << PTE0_PL ) | \
|
||
|
|
( d << PTE0_D ) | \
|
||
|
|
( a << PTE0_A ) | \
|
||
|
|
( ma << PTE0_MA ) | \
|
||
|
|
( p << PTE0_P ) \
|
||
|
|
)
|
||
|
|
|
||
|
|
#define ITIR(ppn48_63, key, ps) \
|
||
|
|
( ( ps << ITIR_PS ) | \
|
||
|
|
( key << ITIR_KEY ) | \
|
||
|
|
( ppn48_63 << ITIR_PPN ) \
|
||
|
|
)
|
||
|
|
|
||
|
|
//
|
||
|
|
// Macro to generate mask value from bit position. The result is a
|
||
|
|
// 64-bit.
|
||
|
|
//
|
||
|
|
#define BITMASK(bp, value) (value << bp)
|
||
|
|
|
||
|
|
#define BUNDLE_SIZE 16
|
||
|
|
#define SPURIOUS_INT 0xF
|
||
|
|
|
||
|
|
#define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
|
||
|
|
|
||
|
|
#define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;
|
||
|
|
|
||
|
|
#endif
|