mirror of https://github.com/acidanthera/audk.git
176 lines
7.9 KiB
C
176 lines
7.9 KiB
C
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/*++
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Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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I2CRegs.h
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Abstract:
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Register Definitions for I2C Driver/PEIM.
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--*/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#ifndef I2C_REGS_A0_H
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#define I2C_REGS_A0_H
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//
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// FIFO write workaround value.
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//
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#define FIFO_WRITE_DELAY 2
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//
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// MMIO Register Definitions
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//
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#define R_IC_CON ( 0x00) // I2C Control
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#define B_IC_RESTART_EN BIT5
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#define B_IC_SLAVE_DISABLE BIT6
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#define V_SPEED_STANDARD 0x02
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#define V_SPEED_FAST 0x04
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#define V_SPEED_HIGH 0x06
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#define B_MASTER_MODE BIT0
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#define R_IC_TAR ( 0x04) // I2C Target Address
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#define IC_TAR_10BITADDR_MASTER BIT12
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#define R_IC_SAR ( 0x08) // I2C Slave Address
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#define R_IC_HS_MADDR ( 0x0C) // I2C HS MasterMode Code Address
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#define R_IC_DATA_CMD ( 0x10) // I2C Rx/Tx Data Buffer and Command
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#define B_READ_CMD BIT8 // 1 = read, 0 = write
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#define B_CMD_STOP BIT9 // 1 = STOP
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#define B_CMD_RESTART BIT10 // 1 = IC_RESTART_EN
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#define V_WRITE_CMD_MASK ( 0xFF)
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#define R_IC_SS_SCL_HCNT ( 0x14) // Standard Speed I2C Clock SCL High Count
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#define R_IC_SS_SCL_LCNT ( 0x18) // Standard Speed I2C Clock SCL Low Count
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#define R_IC_FS_SCL_HCNT ( 0x1C) // Full Speed I2C Clock SCL High Count
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#define R_IC_FS_SCL_LCNT ( 0x20) // Full Speed I2C Clock SCL Low Count
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#define R_IC_HS_SCL_HCNT ( 0x24) // High Speed I2C Clock SCL High Count
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#define R_IC_HS_SCL_LCNT ( 0x28) // High Speed I2C Clock SCL Low Count
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#define R_IC_INTR_STAT ( 0x2C) // I2C Inetrrupt Status
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#define R_IC_INTR_MASK ( 0x30) // I2C Interrupt Mask
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#define I2C_INTR_GEN_CALL BIT11 // General call received
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#define I2C_INTR_START_DET BIT10
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#define I2C_INTR_STOP_DET BIT9
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#define I2C_INTR_ACTIVITY BIT8
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#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
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#define I2C_INTR_TX_EMPTY BIT4
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#define I2C_INTR_TX_OVER BIT3
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#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
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#define I2C_INTR_RX_OVER BIT1
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#define I2C_INTR_RX_UNDER BIT0
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#define R_IC_RAW_INTR_STAT ( 0x34) // I2C Raw Interrupt Status
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#define R_IC_RX_TL ( 0x38) // I2C Receive FIFO Threshold
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#define R_IC_TX_TL ( 0x3C) // I2C Transmit FIFO Threshold
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#define R_IC_CLR_INTR ( 0x40) // Clear Combined and Individual Interrupts
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#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Interrupt
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#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinterrupt
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#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER interrupt
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#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ interrupt
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#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT interrupt
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#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE interrupt
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#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY interrupt
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#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET interrupt
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#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET interrupt
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#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL interrupt
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#define R_IC_ENABLE ( 0x6C) // I2C Enable
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#define R_IC_STATUS ( 0x70) // I2C Status
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#define R_IC_SDA_HOLD ( 0x7C) // I2C IC_DEFAULT_SDA_HOLD//16bits
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#define STAT_MST_ACTIVITY BIT5 // Master FSM Activity Status.
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#define STAT_RFF BIT4 // RX FIFO is completely full
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#define STAT_RFNE BIT3 // RX FIFO is not empty
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#define STAT_TFE BIT2 // TX FIFO is completely empty
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#define STAT_TFNF BIT1 // TX FIFO is not full
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#define R_IC_TXFLR ( 0x74) // Transmit FIFO Level Register
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#define R_IC_RXFLR ( 0x78) // Receive FIFO Level Register
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#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2C Transmit Abort Status Register
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#define R_IC_SLV_DATA_NACK_ONLY ( 0x84) // Generate SLV_DATA_NACK Register
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#define R_IC_DMA_CR ( 0x88) // DMA Control Register
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#define R_IC_DMA_TDLR ( 0x8C) // DMA Transmit Data Level
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#define R_IC_DMA_RDLR ( 0x90) // DMA Receive Data Level
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#define R_IC_SDA_SETUP ( 0x94) // I2C SDA Setup Register
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#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2C ACK General Call Register
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#define R_IC_ENABLE_STATUS ( 0x9C) // I2C Enable Status Register
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#define R_IC_COMP_PARAM ( 0xF4) // Component Parameter Register
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#define R_IC_COMP_VERSION ( 0xF8) // Component Version ID
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#define R_IC_COMP_TYPE ( 0xFC) // Component Type
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#define R_IC_CLK_GATE ( 0xC0) // Clock Gate
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#define I2C_SS_SCL_HCNT_VALUE_100M 0x1DD
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#define I2C_SS_SCL_LCNT_VALUE_100M 0x1E4
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#define I2C_FS_SCL_HCNT_VALUE_100M 0x54
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#define I2C_FS_SCL_LCNT_VALUE_100M 0x9a
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#define I2C_HS_SCL_HCNT_VALUE_100M 0x7
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#define I2C_HS_SCL_LCNT_VALUE_100M 0xE
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#define IC_TAR_10BITADDR_MASTER BIT12
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#define FIFO_SIZE 32
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#define R_IC_INTR_STAT ( 0x2C) // I2c Inetrrupt Status
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#define R_IC_INTR_MASK ( 0x30) // I2c Interrupt Mask
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#define I2C_INTR_GEN_CALL BIT11 // General call received
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#define I2C_INTR_START_DET BIT10
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#define I2C_INTR_STOP_DET BIT9
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#define I2C_INTR_ACTIVITY BIT8
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#define I2C_INTR_TX_ABRT BIT6 // Set on NACK
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#define I2C_INTR_TX_EMPTY BIT4
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#define I2C_INTR_TX_OVER BIT3
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#define I2C_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
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#define I2C_INTR_RX_OVER BIT1
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#define I2C_INTR_RX_UNDER BIT0
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EFI_STATUS ProgramPciLpssI2C (
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IN UINT8 BusNo
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);
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EFI_STATUS ByteReadI2C_Basic(
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IN UINT8 BusNo,
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IN UINT8 SlaveAddress,
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IN UINTN ReadBytes,
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OUT UINT8 *ReadBuffer,
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IN UINT8 Start,
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IN UINT8 End
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);
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EFI_STATUS ByteWriteI2C_Basic(
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IN UINT8 BusNo,
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IN UINT8 SlaveAddress,
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IN UINTN WriteBytes,
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IN UINT8 *WriteBuffer,
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IN UINT8 Start,
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IN UINT8 End
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);
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EFI_STATUS ByteReadI2C(
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IN UINT8 BusNo,
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IN UINT8 SlaveAddress,
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IN UINT8 Offset,
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IN UINTN ReadBytes,
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OUT UINT8 *ReadBuffer
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);
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EFI_STATUS ByteWriteI2C(
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IN UINT8 BusNo,
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IN UINT8 SlaveAddress,
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IN UINT8 Offset,
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IN UINTN WriteBytes,
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IN UINT8 *WriteBuffer
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);
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#endif // I2C_REGS_A0_H
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