mirror of https://github.com/acidanthera/audk.git
156 lines
7.8 KiB
C
156 lines
7.8 KiB
C
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/**
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Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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@file
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PchRegsSmbus.h
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@brief
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Register names for VLV Smbus Device.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values of bits within the registers
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
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- Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without <generation_name> inserted.
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**/
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#ifndef _PCH_REGS_SMBUS_H_
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#define _PCH_REGS_SMBUS_H_
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///
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/// SMBus Controller Registers (D31:F3)
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///
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#define PCI_DEVICE_NUMBER_PCH_SMBUS 31
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#define PCI_FUNCTION_NUMBER_PCH_SMBUS 3
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#define R_PCH_SMBUS_VENDOR_ID 0x00 // Vendor ID
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#define V_PCH_SMBUS_VENDOR_ID V_PCH_INTEL_VENDOR_ID // Intel Vendor ID
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#define R_PCH_SMBUS_DEVICE_ID 0x02 // Device ID
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#define V_PCH_SMBUS_DEVICE_ID 0x0F12
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#define R_PCH_SMBUS_PCICMD 0x04 // CMD register enables/disables, Memory/IO space access and interrupt
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#define B_PCH_SMBUS_PCICMD_INTR_DIS BIT10 // Interrupt Disable
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#define B_PCH_SMBUS_PCICMD_FBE BIT9 // FBE - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_SERR_EN BIT8 // SERR Enable - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_WCC BIT7 // Wait Cycle Control - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_PER BIT6 // Parity Error - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_VPS BIT5 // VGA Palette Snoop - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_PMWE BIT4 // Postable Memory Write Enable - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_SCE BIT3 // Special Cycle Enable - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_BME BIT2 // Bus Master Enable - reserved as '0'
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#define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable
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#define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable
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#define R_PCH_SMBUS_BASE 0x20 // The I/O memory bar
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#define B_PCH_SMBUS_BASE_BAR 0x0000FFE0 // Base Address
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#define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator
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#define R_PCH_SMBUS_SVID 0x2C // Subsystem Vendor ID
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#define B_PCH_SMBUS_SVID 0xFFFF // Subsystem Vendor ID
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//
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// SMBus I/O Registers
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//
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#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W
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#define B_PCH_SMBUS_HSTS_ALL 0xFF
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#define B_PCH_SMBUS_BYTE_DONE_STS BIT7 // Byte Done Status
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#define B_PCH_SMBUS_IUS BIT6 // In Use Status
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#define B_PCH_SMBUS_SMBALERT_STS BIT5 // SMBUS Alert
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#define B_PCH_SMBUS_FAIL BIT4 // Failed
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#define B_PCH_SMBUS_BERR BIT3 // Bus Error
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#define B_PCH_SMBUS_DERR BIT2 // Device Error
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#define B_PCH_SMBUS_ERRORS (B_PCH_SMBUS_FAIL | B_PCH_SMBUS_BERR | B_PCH_SMBUS_DERR)
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#define B_PCH_SMBUS_INTR BIT1 // Interrupt
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#define B_PCH_SMBUS_HBSY BIT0 // Host Busy
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#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W
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#define B_PCH_SMBUS_PEC_EN BIT7 // Packet Error Checking Enable
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#define B_PCH_SMBUS_START BIT6 // Start
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#define B_PCH_SMBUS_LAST_BYTE BIT5 // Last Byte
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#define B_PCH_SMBUS_SMB_CMD 0x1C // SMB Command
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#define V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS 0x1C // Block Process
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#define V_PCH_SMBUS_SMB_CMD_IIC_READ 0x18 // I2C Read
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#define V_PCH_SMBUS_SMB_CMD_BLOCK 0x14 // Block
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#define V_PCH_SMBUS_SMB_CMD_PROCESS_CALL 0x10 // Process Call
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#define V_PCH_SMBUS_SMB_CMD_WORD_DATA 0x0C // Word Data
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#define V_PCH_SMBUS_SMB_CMD_BYTE_DATA 0x08 // Byte Data
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#define V_PCH_SMBUS_SMB_CMD_BYTE 0x04 // Byte
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#define V_PCH_SMBUS_SMB_CMD_QUICK 0x00 // Quick
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#define B_PCH_SMBUS_KILL BIT1 // Kill
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#define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable
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#define R_PCH_SMBUS_HCMD 0x03 // Host Command Register R/W
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#define B_PCH_SMBUS_HCMD 0xFF // Command to be transmitted
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#define R_PCH_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W
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#define B_PCH_SMBUS_ADDRESS 0xFE // 7-bit address of the targeted slave
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#define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = write
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#define B_PCH_SMBUS_RW_SEL_READ 0x01 // Read
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#define B_PCH_SMBUS_RW_SEL_WRITE 0x00 // Write
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//
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#define R_PCH_SMBUS_HD0 0x05 // Data 0 Register R/W
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#define R_PCH_SMBUS_HD1 0x06 // Data 1 Register R/W
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#define R_PCH_SMBUS_HBD 0x07 // Host Block Data Register R/W
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#define R_PCH_SMBUS_PEC 0x08 // Packet Error Check Data Register R/W
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#define R_PCH_SMBUS_RSA 0x09 // Receive Slave Address Register R/W
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#define B_PCH_SMBUS_SLAVE_ADDR 0x7F // TCO slave address (Not used, reserved)
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#define R_PCH_SMBUS_SD 0x0A // Receive Slave Data Register R/W
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#define R_PCH_SMBUS_AUXS 0x0C // Auxiliary Status Register R/WC
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#define B_PCH_SMBUS_CRCE BIT0 // CRC Error
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//
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#define R_PCH_SMBUS_AUXC 0x0D // Auxiliary Control Register R/W
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#define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer
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#define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC
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#define R_PCH_SMBUS_SMLC 0x0E // SMLINK Pin Control Register R/W
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#define B_PCH_SMBUS_SMLINK_CLK_CTL BIT2 // Not supported
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#define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported
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#define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported
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#define R_PCH_SMBUS_SMBC 0x0F // SMBus Pin Control Register R/W
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#define B_PCH_SMBUS_SMBCLK_CTL BIT2 // SMBCLK Control
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#define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status
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#define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status
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#define R_PCH_SMBUS_SSTS 0x10 // Slave Status Register R/WC
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#define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status
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#define R_PCH_SMBUS_SCMD 0x11 // Slave Command Register R/W
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#define B_PCH_SMBUS_SMBALERT_DIS BIT2 // Not supported
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#define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
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#define B_PCH_SMBUS_HOST_NOTIFY_INTREN BIT0 // Host Notify Interrupt Enable
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#define R_PCH_SMBUS_NDA 0x14 // Notify Device Address Register RO
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#define B_PCH_SMBUS_DEVICE_ADDRESS 0xFE // Device Address
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#define R_PCH_SMBUS_NDLB 0x16 // Notify Data Low Byte Register RO
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#define R_PCH_SMBUS_NDHB 0x17 // Notify Data High Byte Register RO
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#endif
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