mirror of https://github.com/acidanthera/audk.git
123 lines
4.4 KiB
C
123 lines
4.4 KiB
C
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/** @file
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Multiplatform initialization.
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Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <MultiPlatformLib.h>
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/**
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Platform Type detection. Because the PEI globle variable
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is in the flash, it could not change directly.So use
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2 PPIs to distinguish the platform type.
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@param FfsHeader Pointer to Firmware File System file header.
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@param PeiServices General purpose services available to every PEIM.
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@retval EFI_SUCCESS Memory initialization completed successfully.
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@retval Others All other error conditions encountered result in an ASSERT.
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**/
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EFI_STATUS
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MultiPlatformInfoInit (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob
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)
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{
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UINT32 PcieLength;
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EFI_STATUS Status;
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PlatformInfoHob->IohSku = MmPci16(0, MC_BUS, MC_DEV, MC_FUN, PCI_DEVICE_ID_OFFSET);
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PlatformInfoHob->IohRevision = MmPci8(0, MC_BUS, MC_DEV, MC_FUN, PCI_REVISION_ID_OFFSET);
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//
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// Update ICH Type
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//
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//
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// Device ID
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//
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PlatformInfoHob->IchSku = PchLpcPciCfg16(PCI_DEVICE_ID_OFFSET);
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PlatformInfoHob->IchRevision = PchLpcPciCfg8(PCI_REVISION_ID_OFFSET);
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//
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//64MB
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//
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PcieLength = 0x04000000;
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//
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// Don't support BASE above 4GB currently.
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//
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PlatformInfoHob->PciData.PciExpressSize = PcieLength;
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PlatformInfoHob->PciData.PciExpressBase = PcdGet64 (PcdPciExpressBaseAddress);
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PlatformInfoHob->PciData.PciResourceMem32Base = (UINT32) (PlatformInfoHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN);
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PlatformInfoHob->PciData.PciResourceMem32Limit = (UINT32) (PlatformInfoHob->PciData.PciExpressBase -1);
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PlatformInfoHob->PciData.PciResourceMem64Base = RES_MEM64_36_BASE;
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PlatformInfoHob->PciData.PciResourceMem64Limit = RES_MEM64_36_LIMIT;
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PlatformInfoHob->CpuData.CpuAddressWidth = 36;
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PlatformInfoHob->MemData.MemMir0 = PlatformInfoHob->PciData.PciResourceMem64Base;
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PlatformInfoHob->MemData.MemMir1 = PlatformInfoHob->PciData.PciResourceMem64Limit + 1;
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PlatformInfoHob->PciData.PciResourceMinSecBus = 1; //can be changed by SystemConfiguration->PciMinSecondaryBus;
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//
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// Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base.
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//
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if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.PciResourceMem32Base ) {
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PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciResourceMem32Base;
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} else {
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PlatformInfoHob->MemData.MemMaxTolm = (UINT32) PlatformInfoHob->PciData.PciExpressBase;
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}
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PlatformInfoHob->MemData.MemTolm = PlatformInfoHob->MemData.MemMaxTolm;
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//
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// Platform PCI MMIO Size in unit of 1MB.
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//
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PlatformInfoHob->MemData.MmioSize = 0x1000 - (UINT16)(PlatformInfoHob->MemData.MemMaxTolm >> 20);
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//
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// Enable ICH IOAPIC
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//
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PlatformInfoHob->SysData.SysIoApicEnable = ICH_IOAPIC;
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DEBUG ((EFI_D_ERROR, "PlatformFlavor is %x (%x=tablet,%x=mobile,%x=desktop)\n", PlatformInfoHob->PlatformFlavor,FlavorTablet,FlavorMobile,FlavorDesktop));
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//
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// Get Platform Info and fill the Hob.
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//
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PlatformInfoHob->RevisonId = PLATFORM_INFO_HOB_REVISION;
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//
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// Get GPIO table
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//
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Status = MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob);
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//
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// Program GPIO
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//
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Status = MultiPlatformGpioProgram (PeiServices, PlatformInfoHob);
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//
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// Update OemId
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//
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Status = InitializeBoardOemId (PeiServices, PlatformInfoHob);
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Status = InitializeBoardSsidSvid (PeiServices, PlatformInfoHob);
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return EFI_SUCCESS;
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}
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