mirror of https://github.com/acidanthera/audk.git
258 lines
10 KiB
C
258 lines
10 KiB
C
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/** @file
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Memory controller configuration.
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Copyright (c) 2013-2015 Intel Corporation.
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __DDR_MEMORY_CONTROLLER_H__
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#define __DDR_MEMORY_CONTROLLER_H__
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//
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// DDR timing data definitions.
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// These are used to create bitmaps of valid timing configurations.
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//
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#define DUAL_CHANNEL_DDR_TIMING_DATA_FREQUENCY_UNKNOWN 0xFF
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#define DUAL_CHANNEL_DDR_TIMING_DATA_REFRESH_RATE_UNKNOWN 0xFF
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_20 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_25 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_30 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TCL_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_02 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_03 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_04 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRCD_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_02 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_03 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_04 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRP_ALL 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_05 0x05
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_06 0x04
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_07 0x03
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_08 0x02
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_09 0x01
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_10 0x00
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#define DUAL_CHANNEL_DDR_TIMING_DATA_TRAS_ALL 0x07
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#define DUAL_CHANNEL_DDR_DATA_TYPE_REGISTERED 0x01
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#define DUAL_CHANNEL_DDR_DATA_TYPE_UNREGISTERED 0x02
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#define DUAL_CHANNEL_DDR_DATA_TYPE_BUFFERED 0x04
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#define DUAL_CHANNEL_DDR_DATA_TYPE_UNBUFFERED 0x08
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#define DUAL_CHANNEL_DDR_DATA_TYPE_SDR 0x10
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#define DUAL_CHANNEL_DDR_DATA_TYPE_DDR 0x20
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//
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// Maximum number of SDRAM channels supported by the memory controller
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//
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#define MAX_CHANNELS 1
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//
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// Maximum number of DIMM sockets supported by the memory controller
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//
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#define MAX_SOCKETS 1
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//
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// Maximum number of sides supported per DIMM
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//
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#define MAX_SIDES 2
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//
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// Maximum number of "Socket Sets", where a "Socket Set is a set of matching
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// DIMM's from the various channels
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//
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#define MAX_SOCKET_SETS 2
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//
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// Maximum number of rows supported by the memory controller
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//
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#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS)
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//
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// Maximum number of memory ranges supported by the memory controller
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//
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#define MAX_RANGES (MAX_ROWS + 5)
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//
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// Maximum Number of Log entries
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//
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#define MEMORY_LOG_MAX_INDEX 16
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typedef struct _MEMORY_LOG_ENTRY {
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EFI_STATUS_CODE_VALUE Event;
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EFI_STATUS_CODE_TYPE Severity;
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UINT8 Data;
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} MEMORY_LOG_ENTRY;
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typedef struct _MEMORY_LOG {
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UINT8 Index;
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MEMORY_LOG_ENTRY Entry[MEMORY_LOG_MAX_INDEX];
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} MEMORY_LOG;
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//
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// Defined ECC types
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//
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#define DUAL_CHANNEL_DDR_ECC_TYPE_NONE 0x01 // No error checking
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#define DUAL_CHANNEL_DDR_ECC_TYPE_EC 0x02 // Error checking only
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#define DUAL_CHANNEL_DDR_ECC_TYPE_SECC 0x04 // Software Scrubbing ECC
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#define DUAL_CHANNEL_DDR_ECC_TYPE_HECC 0x08 // Hardware Scrubbing ECC
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#define DUAL_CHANNEL_DDR_ECC_TYPE_CKECC 0x10 // Chip Kill ECC
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//
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// Row configuration status values
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//
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_SUCCESS 0x00 // No error
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNKNOWN 0x01 // Pattern mismatch, no memory
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_UNSUPPORTED 0x02 // Memory type not supported
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_ADDRESS_ERROR 0x03 // Row/Col/Bnk mismatch
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_ECC_ERROR 0x04 // Received ECC error
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_NOT_PRESENT 0x05 // Row is not present
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#define DUAL_CHANNEL_DDR_ROW_CONFIG_DISABLED 0x06 // Row is disabled
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//
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// Memory range types
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//
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typedef enum {
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DualChannelDdrMainMemory,
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DualChannelDdrSmramCacheable,
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DualChannelDdrSmramNonCacheable,
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DualChannelDdrGraphicsMemoryCacheable,
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DualChannelDdrGraphicsMemoryNonCacheable,
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DualChannelDdrReservedMemory,
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DualChannelDdrMaxMemoryRangeType
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} DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE;
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//
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// Memory map range information
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//
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typedef struct {
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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EFI_PHYSICAL_ADDRESS CpuAddress;
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EFI_PHYSICAL_ADDRESS RangeLength;
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DUAL_CHANNEL_DDR_MEMORY_RANGE_TYPE Type;
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} DUAL_CHANNEL_DDR_MEMORY_MAP_RANGE;
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typedef struct {
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unsigned dramType :1; /**< Type: 0 = RESERVED; 1 = DDR2 */
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unsigned dramWidth :1; /**< Width: 0 = x8; 1 = x16 */
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unsigned dramDensity :2; /**< Density: 00b = 2Gb; 01b = 1Gb; 10b = 512Mb; 11b = 256Mb */
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unsigned dramSpeed :1; /**< Speed Grade: 0 = RESERVED; 1 = 800MT/s;*/
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unsigned dramTimings :3; /**< Timings: 4-4-4, 5-5-5, 6-6-6 */
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unsigned dramRanks :1; /**< Ranks: 0 = Single Rank; 1 = Dual Rank */
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} DramGeometry; /**< DRAM Geometry Descriptor */
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typedef union _RegDRP {
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UINT32 raw;
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struct {
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unsigned rank0Enabled :1; /**< Rank 0 Enable */
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unsigned rank0DevWidth :2; /**< DRAM Device Width (x8,x16) */
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unsigned rank0DevDensity :2; /**< DRAM Device Density (256Mb,512Mb,1Gb,2Gb) */
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unsigned reserved2 :1;
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unsigned rank1Enabled :1; /**< Rank 1 Enable */
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unsigned reserved3 :5;
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unsigned dramType :1; /**< DRAM Type (0=DDR2) */
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unsigned reserved4 :5;
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unsigned reserved5 :14;
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} field;
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} RegDRP; /**< DRAM Rank Population and Interface Register */
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typedef union {
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UINT32 raw;
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struct {
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unsigned dramFrequency :3; /**< DRAM Frequency (000=RESERVED,010=667,011=800) */
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unsigned tRP :2; /**< Precharge to Activate Delay (3,4,5,6) */
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unsigned reserved1 :1;
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unsigned tRCD :2; /**< Activate to CAS Delay (3,4,5,6) */
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unsigned reserved2 :1;
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unsigned tCL :2; /**< CAS Latency (3,4,5,6) */
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unsigned reserved3 :21;
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} field;
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} RegDTR0; /**< DRAM Timing Register 0 */
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typedef union {
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UINT32 raw;
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struct {
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unsigned tWRRD_dly :2; /**< Additional Write to Read Delay (0,1,2,3) */
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unsigned reserved1 :1;
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unsigned tRDWR_dly :2; /**< Additional Read to Write Delay (0,1,2,3) */
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unsigned reserved2 :1;
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unsigned tRDRD_dr_dly :1; /**< Additional Read to Read Delay (1,2) */
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unsigned reserved3 :1;
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unsigned tRD_dly :3; /**< Additional Read Data Sampling Delay (0-7) */
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unsigned reserved4 :1;
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unsigned tRCVEN_halfclk_dly :4; /**< Additional RCVEN Half Clock Delay Control */
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unsigned reserved5 :1;
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unsigned readDqDelay :2; /**< Read DQ Delay */
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unsigned reserved6 :13;
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} field;
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} RegDTR1; /**< DRAM Timing Register 1 */
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typedef union {
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UINT32 raw;
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struct {
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unsigned ckStaticDisable :1; /**< CK/CK# Static Disable */
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unsigned reserved1 :3;
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unsigned ckeStaticDisable :2; /**< CKE Static Disable */
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unsigned reserved2 :8;
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unsigned refreshPeriod :2; /**< Refresh Period (disabled,128clks,3.9us,7.8us) */
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unsigned refreshQueueDepth :2; /**< Refresh Queue Depth (1,2,4,8) */
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unsigned reserved5 :13;
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unsigned initComplete :1; /**< Initialization Complete */
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} field;
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} RegDCO;
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//
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// MRC Data Structure
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//
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typedef struct {
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RegDRP drp;
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RegDTR0 dtr0;
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RegDTR1 dtr1;
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RegDCO dco;
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UINT32 reg0104;
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UINT32 reg0120;
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UINT32 reg0121;
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UINT32 reg0123;
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UINT32 reg0111;
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UINT32 reg0130;
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UINT8 refreshPeriod; /**< Placeholder for the chosen refresh
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* period. This value will NOT be
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* programmed into DCO until all
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* initialization is done.
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*/
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UINT8 ddr2Odt; /**< 0 = Disabled, 1 = 75 ohm, 2 = 150ohm, 3 = 50ohm */
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UINT8 sku; /**< Detected QuarkNcSocId SKU */
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UINT8 capabilities; /**< Capabilities Available on this part */
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UINT8 state; /**< NORMAL_BOOT, S3_RESUME */
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UINT32 memSize; /**< Memory size */
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UINT16 pmBase; /**< PM Base */
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UINT16 mrcVersion; /**< MRC Version */
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UINT32 hecbase; /**< HECBASE shifted left 16 bits */
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DramGeometry geometry; /**< DRAM Geometry */
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} MRC_DATA_STRUCTURE; /**< QuarkNcSocId Memory Parameters for MRC */
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typedef struct _EFI_MEMINIT_CONFIG_DATA {
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MRC_DATA_STRUCTURE MrcData;
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} EFI_MEMINIT_CONFIG_DATA;
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#endif
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