mirror of https://github.com/acidanthera/audk.git
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
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/** @file
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SMM CPU misc functions for x64 arch specific.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "PiSmmCpuDxeSmm.h"
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/**
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Initialize Gdt for all processors.
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@param[in] Cr3 CR3 value.
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@param[out] GdtStepSize The step size for GDT table.
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@return GdtBase for processor 0.
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GdtBase for processor X is: GdtBase + (GdtStepSize * X)
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**/
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VOID *
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InitGdt (
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IN UINTN Cr3,
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OUT UINTN *GdtStepSize
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)
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{
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UINTN Index;
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IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
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UINTN TssBase;
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UINTN GdtTssTableSize;
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UINT8 *GdtTssTables;
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UINTN GdtTableStepSize;
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//
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// For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
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// on each SMI entry.
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//
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GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
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GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
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ASSERT (GdtTssTables != NULL);
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GdtTableStepSize = GdtTssTableSize;
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for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
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CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
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//
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// Fixup TSS descriptors
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//
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TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
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GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
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GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
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GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
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GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);
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if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
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//
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// Setup top of known good stack as IST1 for each processor.
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//
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*(UINTN *)(TssBase + TSS_X64_IST1_OFFSET) = (mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize);
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}
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}
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*GdtStepSize = GdtTableStepSize;
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return GdtTssTables;
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}
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