mirror of https://github.com/acidanthera/audk.git
337 lines
16 KiB
C
337 lines
16 KiB
C
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/** @file
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SPI flash device description.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "SpiFlashDevice.h"
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#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))
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SPI_INIT_TABLE mSpiInitTable[] = {
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//
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// Macronix 32Mbit part
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//
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{
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SPI_MX25L3205_ID1,
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SPI_MX25L3205_ID2,
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SPI_MX25L3205_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Winbond 32Mbit part
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//
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{
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SPI_W25X32_ID1,
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SF_DEVICE_ID0_W25QXX,
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SF_DEVICE_ID1_W25Q32,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Winbond 32Mbit part
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//
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{
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SPI_W25X32_ID1,
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SPI_W25X32_ID2,
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SPI_W25X32_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Atmel 32Mbit part
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//
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{
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SPI_AT26DF321_ID1,
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SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel
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SPI_AT26DF321_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Intel 32Mbit part bottom boot
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//
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{
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SPI_QH25F320_ID1,
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SPI_QH25F320_ID2,
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SPI_QH25F320_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_ENABLE
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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0, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// SST 64Mbit part
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//
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{
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SPI_SST25VF080B_ID1, // VendorId
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SF_DEVICE_ID0_25VF064C, // DeviceId 0
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SF_DEVICE_ID1_25VF064C, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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0x800000 - FLASH_SIZE, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// NUMONYX 64Mbit part
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//
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{
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SF_VENDOR_ID_NUMONYX, // VendorId
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SF_DEVICE_ID0_M25PX64, // DeviceId 0
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SF_DEVICE_ID1_M25PX64, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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0x800000 - FLASH_SIZE, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Atmel 64Mbit part
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//
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{
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SF_VENDOR_ID_ATMEL, // VendorId
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SF_DEVICE_ID0_AT25DF641, // DeviceId 0
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SF_DEVICE_ID1_AT25DF641, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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0x800000 - FLASH_SIZE, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Spansion 64Mbit part
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//
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{
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SF_VENDOR_ID_SPANSION, // VendorId
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SF_DEVICE_ID0_S25FL064K, // DeviceId 0
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SF_DEVICE_ID1_S25FL064K, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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0x800000 - FLASH_SIZE, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Macronix 64Mbit part bottom boot
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//
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{
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SF_VENDOR_ID_MX, // VendorId
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SF_DEVICE_ID0_25L6405D, // DeviceId 0
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SF_DEVICE_ID1_25L6405D, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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0x800000 - FLASH_SIZE, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Winbond 64Mbit part bottom boot
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//
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{
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SPI_W25X64_ID1,
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SF_DEVICE_ID0_W25QXX,
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SF_DEVICE_ID1_W25Q64,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||
|
|
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||
|
|
},
|
||
|
|
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||
|
|
FLASH_SIZE // BIOS image size in flash
|
||
|
|
},
|
||
|
|
//
|
||
|
|
// Winbond 64Mbit part bottom boot
|
||
|
|
//
|
||
|
|
{
|
||
|
|
SPI_W25X64_ID1,
|
||
|
|
SPI_W25X64_ID2,
|
||
|
|
SPI_W25X64_ID3,
|
||
|
|
{
|
||
|
|
SPI_COMMAND_WRITE_ENABLE,
|
||
|
|
SPI_COMMAND_WRITE_S_EN
|
||
|
|
},
|
||
|
|
{
|
||
|
|
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||
|
|
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||
|
|
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||
|
|
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||
|
|
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||
|
|
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||
|
|
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||
|
|
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||
|
|
},
|
||
|
|
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||
|
|
FLASH_SIZE // BIOS image size in flash
|
||
|
|
},
|
||
|
|
//
|
||
|
|
// Intel 64Mbit part bottom boot
|
||
|
|
//
|
||
|
|
{
|
||
|
|
SPI_QH25F640_ID1,
|
||
|
|
SPI_QH25F640_ID2,
|
||
|
|
SPI_QH25F640_ID3,
|
||
|
|
{
|
||
|
|
SPI_COMMAND_WRITE_ENABLE,
|
||
|
|
SPI_COMMAND_WRITE_S_EN
|
||
|
|
},
|
||
|
|
{
|
||
|
|
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
|
||
|
|
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
|
||
|
|
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
|
||
|
|
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
|
||
|
|
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
|
||
|
|
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
|
||
|
|
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
|
||
|
|
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
|
||
|
|
},
|
||
|
|
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||
|
|
FLASH_SIZE // BIOS image size in flash
|
||
|
|
}
|
||
|
|
};
|