mirror of https://github.com/acidanthera/audk.git
383 lines
9.2 KiB
C
383 lines
9.2 KiB
C
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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Module Name:
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IchS3Save.c
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Abstract:
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SMM S3 handler Driver implementation file
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Revision History
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**/
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#include "SmmPlatform.h"
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extern UINT16 mAcpiBaseAddr;
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EFI_PHYSICAL_ADDRESS mRuntimeScriptTableBase;
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EFI_STATUS
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InitRuntimeScriptTable (
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINT32 VarAttrib;
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UINTN VarSize;
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ACPI_VARIABLE_SET_COMPATIBILITY *AcpiVariableBase;
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//
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// Allocate runtime ACPI script table space. We need it to save some
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// settings done by CSM, which runs after normal script table closed
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//
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Status = gBS->AllocatePages (
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AllocateAnyPages,
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EfiACPIReclaimMemory,
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1,
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&mRuntimeScriptTableBase
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);
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if (EFI_ERROR(Status)) {
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return EFI_OUT_OF_RESOURCES ;
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}
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//
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// Save runtime script table base into global ACPI variable
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//
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VarAttrib = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS
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| EFI_VARIABLE_NON_VOLATILE;
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VarSize = sizeof (UINTN);
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Status = SystemTable->RuntimeServices->GetVariable (
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ACPI_GLOBAL_VARIABLE,
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&gEfiAcpiVariableCompatiblityGuid,
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&VarAttrib,
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&VarSize,
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&AcpiVariableBase
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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AcpiVariableBase->RuntimeScriptTableBase = mRuntimeScriptTableBase;
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return EFI_SUCCESS;
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}
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EFI_STATUS
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SaveRuntimeScriptTable (
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VOID
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)
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{
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SMM_PCI_IO_ADDRESS PciAddress;
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UINT32 Data32;
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UINT16 Data16;
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UINT8 Data8;
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UINT8 Mask;
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UINTN Index;
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UINTN Offset;
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UINT8 RegTable[] = {
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//
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//Bus , Dev, Func, DMI
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//
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0x00 , 0x00, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x00 , 0x08, 0x00, 0x00, 0x30, 0x00, 0x00, 0xa0,
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//
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//Bus , Dev, Func, LPC device
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//
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0x00 , 0x1F, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x00 , 0x08, 0x00, 0x07, 0x00, 0x00, 0x90, 0x00,
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//
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//Bus , Dev, Func, PCIE device
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//
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0x00 , 0x1C, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0xC0 , 0x83, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, PCIE device
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//
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0x00 , 0x1C, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x03 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, SATA device
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//
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0x00 , 0x13, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0xf4 , 0xab, 0x27, 0x10, 0xf1, 0x1d, 0x00, 0x40,
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//
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//Bus , Dev, Func, EHCI device
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//
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0x00 , 0x1D, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x10 , 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
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//
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//Bus , Dev, Func, SMBUS device
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//
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0x00 , 0x1f, 0x03,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x10 , 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, SMBUS device
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//
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0x00 , 0x1f, 0x03,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, VGA bus1
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//
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0x01 , 0x00, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x58 , 0x81, 0x18, 0x01, 0xb0, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, VGA bus1
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//
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0x01 , 0x00, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, VGA bus1 function 1
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//
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0x01 , 0x00, 0x01,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x51 , 0x80, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, VGA bus1 function 1
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//
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0x01 , 0x00, 0x01,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x02 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, IGD bus0 function 0
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//
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0x00 , 0x02, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x42 , 0x81, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
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//
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//Bus , Dev, Func, USB bus0 function 0
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//
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0x00 , 0x16, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x32 , 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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//
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//Bus , Dev, Func, HD Audio bus0 function 0
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//
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0x00 , 0x1B, 0x00,
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//
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//00-1F, 20-3F, 40-5F, 60-7F, 80-9F, A0-BF, C0-DF, E0-FF
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//
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0x00 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
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//
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//0xFF indicates the end of the table
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//
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0xFF
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};
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//
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// These registers have to set in byte order
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//
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UINT8 ExtReg[] = { 0x9E, 0x9D }; // SMRAM settings
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//
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// Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
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// and vital to S3 resume. That's why we put save code here
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//
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PciAddress.Bus = 0;
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PciAddress.Device = 0;
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PciAddress.Function = 0;
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PciAddress.ExtendedRegister = 0;
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for (Index = 0; Index < 2; Index++) {
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//
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// Read SRAM setting from Pci(0, 0, 0)
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//
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PciAddress.Register = ExtReg[Index];
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Data8 = MmioRead8 (
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MmPciAddress (0,
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PciAddress.Bus,
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PciAddress.Device,
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PciAddress.Function,
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PciAddress.Register
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)
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);
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//
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// Save latest settings to runtime script table
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//
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S3BootScriptSavePciCfgWrite(
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S3BootScriptWidthUint8,
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*(UINT64*)&PciAddress,
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1,
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&Data8
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);
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}
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//
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// Save PCI-Host bridge settings (0, 0, 0). 0x90, 94 and 9c are changed by CSM
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// and vital to S3 resume. That's why we put save code here
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//
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Index = 0;
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while (RegTable[Index] != 0xFF) {
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PciAddress.Bus = RegTable[Index++];
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PciAddress.Device = RegTable[Index++];
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PciAddress.Function = RegTable[Index++];
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PciAddress.Register = 0;
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PciAddress.ExtendedRegister = 0;
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Data16 = MmioRead16 (
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MmPciAddress (0,
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PciAddress.Bus,
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PciAddress.Device,
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PciAddress.Function,
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PciAddress.Register
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)
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);
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if (Data16 == 0xFFFF) {
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Index+=8;
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continue;
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}
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for (Offset = 0, Mask = 0x01; Offset < 256; Offset+=4, Mask<<=1) {
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if (Mask == 0x00) {
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Mask = 0x01;
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}
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if (RegTable[Index + Offset/32] & Mask ) {
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PciAddress.Register = (UINT8)Offset;
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Data32 = MmioRead32 (MmPciAddress (0, PciAddress.Bus, PciAddress.Device, PciAddress.Function, PciAddress.Register));
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//
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// Save latest settings to runtime script table
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//
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S3BootScriptSavePciCfgWrite (
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S3BootScriptWidthUint32,
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*(UINT64*)&PciAddress,
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1,
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&Data32
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);
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}
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}
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Index += 8;
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}
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//
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// Save I/O ports to S3 script table
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//
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//
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// Selftest KBC
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//
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Data8 = 0xAA;
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S3BootScriptSaveIoWrite (
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S3BootScriptWidthUint8,
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0x64,
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(UINTN)1,
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&Data8
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);
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Data32 = IoRead32(mAcpiBaseAddr + R_PCH_SMI_EN);
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S3BootScriptSaveIoWrite (
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S3BootScriptWidthUint32,
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(mAcpiBaseAddr + R_PCH_SMI_EN),
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1,
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&Data32
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);
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//
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// Save B_ICH_TCO_CNT_LOCK so it will be done on S3 resume path.
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//
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Data16 = IoRead16(mAcpiBaseAddr + R_PCH_TCO_CNT);
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S3BootScriptSaveIoWrite (
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S3BootScriptWidthUint16,
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mAcpiBaseAddr + R_PCH_TCO_CNT,
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1,
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&Data16
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);
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return EFI_SUCCESS;
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}
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