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audk/OvmfPkg/Include/TdxCommondefs.inc

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OvmfPkg: Update Sec to support Tdx RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 There are below major changes in this commit. 1. SecEntry.nasm In TDX BSP and APs goes to the same entry point in SecEntry.nasm. BSP initialize the temporary stack and then jumps to SecMain, just as legacy Ovmf does. APs spin in a modified mailbox loop using initial mailbox structure. Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h. APs wait for command to see if the command is for me. If so execute the command. 2. Sec/SecMain.c When host VMM create the Td guest, the system memory informations are stored in TdHob, which is a memory region described in Tdx metadata. The system memory region in TdHob should be accepted before it can be accessed. So the major task of this patch is to process the TdHobList to accept the memory. After that TDVF follow the standard OVMF flow and jump to PEI phase. PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives no chance for Intel TDX to support 1G page table. To support 1G page table this PCD is set to TRUE in OvmfPkgX64.dsc. TDX_GUEST_SUPPORTED is defined in OvmfPkgX64.dsc. This macro wraps the Tdx specific code. TDX only works on X64, so the code is only valid in X64 arch. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
2021-07-16 10:04:11 +02:00
;------------------------------------------------------------------------------
; @file
; TDX Common defitions used by the APs in mailbox
;
; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
CommandOffset equ 00h
ApicidOffset equ 04h
WakeupVectorOffset equ 08h
OSArgsOffset equ 10h
FirmwareArgsOffset equ 800h
WakeupArgsRelocatedMailBox equ 800h
AcceptPageArgsPhysicalStart equ 800h
AcceptPageArgsPhysicalEnd equ 808h
OvmfPkg: Enable APs to accept memory for TDVF BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4172 TDVF APs once did nothing but spin around to wait for the Wakeup command. This patch enables APs to handle the AcceptPages command. Once APs find the AcceptPages command, it set its stack and jump to the function of ApAcceptMemoryResourceRange (which will be introduced in the following patch). Cc: Erdem Aktas <erdemaktas@google.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Min Xu <min.m.xu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2022-12-20 09:42:39 +01:00
AcceptPageArgsTopStackAddress equ 810h
AcceptPageArgsApStackSize equ 818h
OvmfPkg: Update Sec to support Tdx RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 There are below major changes in this commit. 1. SecEntry.nasm In TDX BSP and APs goes to the same entry point in SecEntry.nasm. BSP initialize the temporary stack and then jumps to SecMain, just as legacy Ovmf does. APs spin in a modified mailbox loop using initial mailbox structure. Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h. APs wait for command to see if the command is for me. If so execute the command. 2. Sec/SecMain.c When host VMM create the Td guest, the system memory informations are stored in TdHob, which is a memory region described in Tdx metadata. The system memory region in TdHob should be accepted before it can be accessed. So the major task of this patch is to process the TdHobList to accept the memory. After that TDVF follow the standard OVMF flow and jump to PEI phase. PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives no chance for Intel TDX to support 1G page table. To support 1G page table this PCD is set to TRUE in OvmfPkgX64.dsc. TDX_GUEST_SUPPORTED is defined in OvmfPkgX64.dsc. This macro wraps the Tdx specific code. TDX only works on X64, so the code is only valid in X64 arch. Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Signed-off-by: Min Xu <min.m.xu@intel.com>
2021-07-16 10:04:11 +02:00
CpuArrivalOffset equ 900h
CpusExitingOffset equ 0a00h
TalliesOffset equ 0a08h
ErrorsOffset equ 0e08h
SIZE_4KB equ 1000h
SIZE_2MB equ 200000h
SIZE_1GB equ 40000000h
PAGE_ACCEPT_LEVEL_4K equ 0
PAGE_ACCEPT_LEVEL_2M equ 1
PAGE_ACCEPT_LEVEL_1G equ 2
TDX_PAGE_ALREADY_ACCEPTED equ 0x00000b0a
TDX_PAGE_SIZE_MISMATCH equ 0xc0000b0b
; Errors of APs in Mailbox
ERROR_NON equ 0
ERROR_INVALID_ACCEPT_PAGE_SIZE equ 1
ERROR_ACCEPT_PAGE_ERROR equ 2
ERROR_INVALID_FALLBACK_PAGE_LEVEL equ 3
MpProtectedModeWakeupCommandNoop equ 0
MpProtectedModeWakeupCommandWakeup equ 1
MpProtectedModeWakeupCommandSleep equ 2
MpProtectedModeWakeupCommandAcceptPages equ 3
MailboxApicIdInvalid equ 0xffffffff
MailboxApicidBroadcast equ 0xfffffffe
%define TDCALL_TDINFO 0x1
%define TDCALL_TDACCEPTPAGE 0x6