mirror of https://github.com/acidanthera/audk.git
97 lines
3.7 KiB
ArmAsm
97 lines
3.7 KiB
ArmAsm
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//++
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// Copyright (c) 2006, Intel Corporation
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// All rights reserved. This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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// Module Name:
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// FlushCacheRange.s
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//
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// Abstract:
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// Assemble routine to flush cache lines
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//
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// Revision History:
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//
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//--
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.file "IpfCpuCache.s"
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#include "IpfMacro.i"
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//#include "IpfDefines.h"
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//
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// Invalidates a range of instruction cache lines in the cache coherency domain
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// of the calling CPU.
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//
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// Invalidates the instruction cache lines specified by Address and Length. If
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// Address is not aligned on a cache line boundary, then entire instruction
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// cache line containing Address is invalidated. If Address + Length is not
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// aligned on a cache line boundary, then the entire instruction cache line
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// containing Address + Length -1 is invalidated. This function may choose to
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// invalidate the entire instruction cache if that is more efficient than
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// invalidating the specified range. If Length is 0, the no instruction cache
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// lines are invalidated. Address is returned.
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//
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// If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
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//
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// @param Address The base address of the instruction cache lines to
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// invalidate. If the CPU is in a physical addressing mode, then
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// Address is a physical address. If the CPU is in a virtual
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// addressing mode, then Address is a virtual address.
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//
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// @param Length The number of bytes to invalidate from the instruction cache.
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//
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// @return Address
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//
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// VOID *
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// EFIAPI
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// IpfFlushCacheRange (
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// IN VOID *Address,
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// IN UINTN Length
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// );
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//
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PROCEDURE_ENTRY (IpfFlushCacheRange)
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NESTED_SETUP (5,8,0,0)
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mov loc2 = ar.lc
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mov loc3 = in0 // Start address.
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mov loc4 = in1;; // Length in bytes.
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cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
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(p6) br.spnt.many DoneFlushingC;;
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add loc4 = loc4,loc3
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mov loc5 = 1;;
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sub loc4 = loc4, loc5 ;; // the End address to flush
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dep loc3 = r0,loc3,0,5
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dep loc4 = r0,loc4,0,5;;
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shr loc3 = loc3,5
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shr loc4 = loc4,5;; // 32 byte cache line
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sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
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// the br.cloop will first execute one time
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mov loc3 = in0
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mov loc5 = 32
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mov ar.lc = loc4;;
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StillFlushingC:
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fc loc3;;
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sync.i;;
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srlz.i;;
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add loc3 = loc5,loc3;;
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br.cloop.sptk.few StillFlushingC;;
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DoneFlushingC:
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mov ar.lc = loc2
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mov r8 = in0 // return *Address
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NESTED_RETURN
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PROCEDURE_EXIT (IpfFlushCacheRange)
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