2016-07-20 15:56:58 +02:00
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## @file
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# MP Initialize Library instance for DXE driver.
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#
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2023-03-01 07:09:52 +01:00
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# Copyright (c) 2016 - 2023, Intel Corporation. All rights reserved.<BR>
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2024-04-12 04:12:06 +02:00
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# Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>
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2019-04-04 01:07:22 +02:00
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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2016-07-20 15:56:58 +02:00
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = DxeMpInitLib
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MODULE_UNI_FILE = DxeMpInitLib.uni
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FILE_GUID = B88F7146-9834-4c55-BFAC-481CC0C33736
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.1
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LIBRARY_CLASS = MpInitLib|DXE_DRIVER
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#
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# The following information is for reference only and not required by the build tools.
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#
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2024-04-12 04:12:06 +02:00
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# VALID_ARCHITECTURES = IA32 X64 LOONGARCH64
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2016-07-20 15:56:58 +02:00
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#
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2016-07-20 16:44:39 +02:00
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[Sources.IA32]
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2021-12-09 04:28:00 +01:00
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Ia32/AmdSev.c
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2023-03-01 07:09:52 +01:00
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Ia32/CreatePageTable.c
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2024-03-20 07:52:05 +01:00
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Ia32/MpFuncs.nasm
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2016-07-20 16:44:39 +02:00
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[Sources.X64]
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2021-12-09 04:28:00 +01:00
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X64/AmdSev.c
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2023-03-01 07:09:52 +01:00
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X64/CreatePageTable.c
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2024-03-20 07:52:05 +01:00
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X64/MpFuncs.nasm
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2016-07-20 16:44:39 +02:00
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2024-04-12 04:12:06 +02:00
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[Sources.IA32, Sources.X64]
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2021-12-09 04:27:30 +01:00
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AmdSev.c
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2016-07-20 15:56:58 +02:00
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DxeMpLib.c
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2024-03-20 07:52:05 +01:00
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Microcode.c
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MpEqu.inc
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2016-07-20 15:56:58 +02:00
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MpLib.c
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MpLib.h
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2023-06-28 10:47:22 +02:00
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MpHandOff.h
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2016-07-20 15:56:58 +02:00
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2024-04-12 04:12:06 +02:00
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[Sources.LoongArch64]
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LoongArch64/DxeMpLib.c
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LoongArch64/MpLib.c
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LoongArch64/MpLib.h
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2016-07-20 15:56:58 +02:00
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[Packages]
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MdePkg/MdePkg.dec
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2016-12-26 09:28:58 +01:00
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MdeModulePkg/MdeModulePkg.dec
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2016-07-20 15:56:58 +02:00
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UefiCpuPkg/UefiCpuPkg.dec
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[LibraryClasses]
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BaseLib
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2024-03-20 07:52:05 +01:00
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CpuLib
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DebugAgentLib
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HobLib
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2016-07-20 15:56:58 +02:00
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MemoryAllocationLib
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2020-04-22 08:50:24 +02:00
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PcdLib
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2024-03-20 07:52:05 +01:00
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SynchronizationLib
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UefiBootServicesTableLib
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2024-04-12 04:12:06 +02:00
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[LibraryClasses.IA32, LibraryClasses.X64]
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2024-03-08 16:32:09 +01:00
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AmdSvsmLib
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2024-04-12 04:12:06 +02:00
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CcExitLib
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LocalApicLib
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MicrocodeLib
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MtrrLib
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2023-03-01 07:09:52 +01:00
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[LibraryClasses.X64]
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CpuPageTableLib
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2016-07-20 15:56:58 +02:00
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2016-12-26 12:13:44 +01:00
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[Protocols]
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gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES
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2016-07-20 15:56:58 +02:00
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[Guids]
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gEfiEventExitBootServicesGuid ## CONSUMES ## Event
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2017-09-25 13:06:17 +02:00
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gEfiEventLegacyBootGuid ## SOMETIMES_CONSUMES ## Event
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UefiCpuPkg/MpInitLib: Not pass microcode info between archs in CPU_MP_DATA
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2465
Commit 89164babec:
UefiCpuPkg/MpInitLib: don't shadow the microcode patch twice.
attempted to use 'MicrocodePatchRegionSize' and 'MicrocodePatchAddress'
fields to avoid loading the microcode patches data into memory again in
the DXE phase.
However, the CPU_MP_DATA structure has members with type 'UINTN' or
pointer before the microcode patch related fields. This may cause issues
when PEI and DXE are of different archs (e.g. PEI - IA32, DXE - x64),
since the microcode patch related fields will have different offsets in
the CPU_MP_DATA structure.
Commit 88bd066166:
UefiCpuPkg/MpInitLib: Relocate microcode patch fields in CPU_MP_DATA
tried to resolve the above-mentioned issue by relocating the fields
'MicrocodePatchRegionSize' and 'MicrocodePatchAddress' before members with
different size between different archs. But it failed to take the case of
pre-built binaries (e.g. FSP) into consideration.
Binaries can be built when the code base had a different version of the
CPU_MP_DATA structure definition. This may cause issues when accessing
these microcode patch related fields, since their offsets are different
(between PEI phase in the binaries and DXE phase in current code
implementation).
This commit will use the newly introduced EDKII microcode patch HOB
instead for the DXE phase to get the information of the loaded microcode
patches data done in the PEI phase. And the 'MicrocodePatchRegionSize' and
'MicrocodePatchAddress' fields in CPU_MP_DATA will not be used to pass
information between phases.
For pre-built binaries, they can be classified into 3 types with regard to
the time when they are being built:
A. Before commit 89164babec
(In other words, 'MicrocodePatchRegionSize' and 'MicrocodePatchAddress'
were not being used to skip microcode load in DXE)
For this case, the EDKII microcode patch HOB will not be produced. This
commit will load the microcode patches data again in DXE. Such behavior is
the same with the code base back then.
B. After commit 89164babec, before commit e1ed55738e
(In other words, 'MicrocodePatchRegionSize' and 'MicrocodePatchAddress'
being used to skip microcode load in DXE, but failed to work properly
between differnt archs.)
For this case, the EDKII microcode patch HOB will not be produced as well.
This commit will also load the microcode patches data again in DXE.
But since commit 89164babec failed to keep the detection and application
of microcode patches working properly in DXE after skipping the load, we
fall back to the origin behavior (that is to load the microcode patches
data again in DXE).
C. After commit e1ed55738e
(In other words, EDKII microcode patch HOB will be produced.)
For this case, it will have the same behavior with the BIOS built from
the current source codes.
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2020-01-22 07:02:05 +01:00
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gEdkiiMicrocodePatchHobGuid ## SOMETIMES_CONSUMES ## HOB
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2024-03-08 16:30:33 +01:00
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gGhcbApicIdsGuid ## SOMETIMES_CONSUMES ## HOB
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2016-07-20 15:56:58 +02:00
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2024-04-12 04:12:06 +02:00
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[Guids.LoongArch64]
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gProcessorResourceHobGuid ## SOMETIMES_CONSUMES ## HOB
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2016-07-20 15:56:58 +02:00
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[Pcd]
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2024-03-20 07:52:05 +01:00
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gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES
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gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES
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gEfiMdePkgTokenSpaceGuid.PcdConfidentialComputingGuestAttr ## CONSUMES
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UefiCpuPkg/MpInitLib DXE: Add PCD to control AP status check interval
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2627
The commit will introduce a static PCD to specify the periodic interval
for checking the AP status when MP services StartupAllAPs() and
StartupThisAP() are being executed in a non-blocking manner. Or in other
words, specifies the interval for callback function CheckApsStatus().
The purpose is to provide the platform owners with the ability to choose
the proper interval value to trigger CheckApsStatus() according to:
A) The number of processors in the system;
B) How MP services (StartupAllAPs & StartupThisAP) being used.
Setting the PCD to a small value means the AP status check callback will
be triggered more frequently, it can benefit the performance for the case
when the BSP uses WaitForEvent() or uses CheckEvent() in a loop to wait
for AP(s) to complete the task, especially when the task can be finished
considerably fast on AP(s).
An example is within function CpuFeaturesInitialize() under
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c,
where BSP will perform the same task with APs and requires all the
processors to finish the task before BSP proceeds to its next task.
Setting the PCD to a big value, on the other hand, can reduce the impact
on BSP by the time being consumed in CheckApsStatus(), especially when the
number of processors is huge so that the time consumed in CheckApsStatus()
is not negligible.
The type of the PCD is UINT32, which means the maximum possible interval
value can be set to:
4,294,967,295 microseconds = 4,295 seconds = 71.58 minutes = 1.19 hours
which should be sufficient for usage.
For least impact, the default value of the new PCD will be the same with
the current interval value. It will be set to 100,000 microseconds, which
is 100 milliseconds.
Unitest done:
A) OS boot successfully;
B) Use debug message to confirm the 'TriggerTime' parameter for the
'SetTimer' service is the same before & after this patch.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Brian J. Johnson <brian.johnson@hpe.com>
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2020-03-13 08:22:19 +01:00
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOMETIMES_CONSUMES
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gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## CONSUMES
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2021-12-09 04:28:00 +01:00
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gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures ## CONSUMES
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UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
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gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOMETIMES_CONSUMES
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2023-07-18 12:05:18 +02:00
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gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi ## CONSUMES
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