mirror of https://github.com/acidanthera/audk.git
103 lines
5.1 KiB
C
103 lines
5.1 KiB
C
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/*++
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Copyright (c) 2010, Apple Inc. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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--*/
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#ifndef __ARM_EB_H__
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#define __ARM_EB_H__
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#include <ArmEb/ArmEbUart.h>
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#include <ArmEb/ArmEbTimer.h>
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///
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/// ARM EB Memory Map
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///
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// 0x00000000 - 0x0FFFFFFF SDRAM 256MB
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// 0x10000000 - 0x100FFFFF System FPGA (config registers) 1MB
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// 0x10000000<30>0x10000FFF 4KB System registers
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// 0x10001000<30>0x10001FFF 4KB System controller
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// 0x10002000<30>0x10002FFF 4KB Two-Wire Serial Bus Interface
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// 0x10003000<30>0x10003FFF 4KB Reserved
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// 0x10004000<30>0x10004FFF 4KB Advanced Audio CODEC Interface
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// 0x10005000<30>0x10005FFF 4KB MultiMedia Card Interface (MCI)
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// 0x10006000<30>0x10006FFF 4KB Keyboard/Mouse Interface 0
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// 0x10007000<30>0x10007FFF 4KB Keyboard/Mouse Interface 1
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// 0x10008000<30>0x10008FFF 4KB Character LCD Interface
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// 0x10009000<30>0x10009FFF 4KB UART 0 Interface
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// 0x1000A000<30>0x1000AFFF 4KB UART 1 Interface
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// 0x1000B000<30>0x1000BFFF 4KB UART 2 Interface
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// 0x1000C000<30>0x1000CFFF 4KB UART 3 Interface
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// 0x1000D000<30>0x1000DFFF 4KB Synchronous Serial Port Interface
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// 0x1000E000<30>0x1000EFFF 4KB Smart Card Interface
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// 0x1000F000<30>0x1000FFFF 4KB Reserved
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// 0x10010000<30>0x10010FFF 4KB Watchdog Interface
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// 0x10011000<30>0x10011FFF 4KB Timer modules 0 and 1 interface (Timer 1 starts at 0x10011020)
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// 0x10012000<30>0x10012FFF 4KB Timer modules 2 and 3 interface (Timer 3 starts at 0x10012020)
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// 0x10013000<30>0x10013FFF 4KB GPIO Interface 0
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// 0x10014000<30>0x10014FFF 4KB GPIO Interface 1
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// 0x10015000<30>0x10015FFF 4KB GPIO Interface 2 (miscellaneous onboard I/O)
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// 0x10016000<30>0x10016FFF 4KB Reserved
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// 0x10017000<30>0x10017FFF 4KB Real Time Clock Interface
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// 0x10018000<30>0x10018FFF 4KB Dynamic Memory Controller configuration
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// 0x10019000<30>0x10019FFF 4KB PCI controller configuration registers
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// 0x1001A000<30>0x1001FFFF 24KB Reserved
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// 0x10020000<30>0x1002FFFF 64KB Color LCD Controller
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// 0x10030000<30>0x1003FFFF 64KB DMA Controller configuration registers
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// 0x10040000<30>0x1004FFFF 64KB Generic Interrupt Controller 1 (nIRQ for tile 1)
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// 0x10050000<30>0x1005FFFF 64KB Generic Interrupt Controller 2 (nFIQ for tile 1)
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// 0x10060000<30>0x1006FFFF 64KB Generic Interrupt Controller 3 (nIRQ for tile 2)
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// 0x10070000<30>0x1007FFFF 64KB Generic Interrupt Controller 4 (nFIQ for tile 2)
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// 0x10080000<30>0x1008FFFF 64KB Static Memory Controller configuration registers
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// 0x100A0000<30>0x100EFFFF 448MB Reserved
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// 0x10090000<30>0x100FFFFF 64KB Debug Access Port (DAP)
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// 0x10100000 - 0x100FFFFF Reserved 3MB
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// 0x10400000 - 0x17FFFFFF System FPGA 124MB
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// 0x18000000 - 0x1FFFFFFF Logic Tile 1 128MB
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// 0x20000000 - 0x3FFFFFFF Reserved 512MB
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// 0x40000000 - 0x7FFFFFFF System FPGA 1GB
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// 0x40000000<30>0x43FFFFFF CS0 NOR flash (nNOR_CS1)
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// 0x44000000<30>0x47FFFFFF CS1 NOR flash (nNOR_CS2)
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// 0x48000000<30>0x4BFFFFFF CS2 SRAM (nSRAMCS)
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// 0x4C000000<30>0x4DFFFFFF CS3 Config flash
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// 0x4E000000<30>0x4EFFFFFF Ethernet
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// 0x4F000000<30>0x4FFFFFFF USB
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// 0x50000000<30>0x53FFFFFF CS4 (nEXPCS) PISMO (nCS0)
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// 0x54000000<30>0x57FFFFFF CS5 (nSTATICCS4) PISMO (nCS1)
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// 0x58000000<30>0x5BFFFFFF CS6 (nSTATICCS5) PISMO (nCS2)
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// 0x5C000000<30>0x5FFFFFFF CS7 (nSTATICCS6) PISMO (nCS3)
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// 0x61000000<30>0x61FFFFFF PCI SelfCfg window
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// 0x62000000<30>0x62FFFFFF PCI Cfg window
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// 0x63000000<30>0x63FFFFFF PCI I/O window
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// 0x64000000<30>0x67FFFFFF PCI memory window 0
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// 0x68000000<30>0x6BFFFFFF PCI memory window 1
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// 0x6C000000<30>0x6FFFFFFF PCI memory window 2
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// 0x70000000 - 0x7FFFFFFF DRAM Mirror
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// 0x80000000 - 0xFFFFFFFF Logic Tile site 2 2GB
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//
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// At reset EB_DRAM_BASE is alaised to EB_CS0_NOR_BASE
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//
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#define EB_DRAM_BASE 0x00000000 // 256 MB DRAM
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#define EB_CONFIG_BASE 0x10000000
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#define EB_CSO_NOR_BASE 0x40000000 // 64 MB NOR FLASH
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#define EB_CS1_NOR_BASE 0x44000000 // 64 MB NOR FLASH
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#define EB_CS2_SRAM 0x48000000 // 2 MB of SRAM
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#define EB_CS3_CONFIG_FLASH 0x4c000000 // 8 MB Config FLASH for FPGA. Not to be used by application code
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#define EB_CS3_ETHERNET 0x4e000000 // 16 MB Ethernet controller
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#define EB_CS4_PISMO_CS0 0x50000000 // Expansion CS0
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#define EB_CS5_PISMO_CS0 0x54000000 // Expansion CS0
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#define EB_CS6_PISMO_CS0 0x58000000 // Expansion CS0
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#define EB_DRAM_REMAP_BASE 0x70000000 // if REMAPSTAT is HIGH alais of EB_DRAM_BASE
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#endif
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