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MdePkg/Register/Amd: expand the SEV MSR to include the SNP definition 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

Define the SEV-SNP MSR bits.

Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Message-Id: <20210519181949.6574-2-brijesh.singh@amd.com>
This commit is contained in:
Brijesh Singh 2021-05-19 13:19:37 -05:00 committed by mergify[bot]
parent dbc22a1785
commit 0095070e70
1 changed files with 6 additions and 1 deletions
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7
MdePkg/Include/Register/Amd/Fam17Msr.h
View File

@ -87,7 +87,12 @@ typedef union {
///
UINT32 SevEsBit:1;
UINT32 Reserved:30;
///
/// [Bit 2] Secure Nested Paging (SevSnp) is enabled
///
UINT32 SevSnpBit:1;
UINT32 Reserved2:29;
} Bits;
///
/// All bit fields as a 32-bit value