mirror of
https://github.com/acidanthera/audk.git
synced 2025-04-08 17:05:09 +02:00
MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 architecture
Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672 Signed-off-by: Abner Chang <abner.chang@hpe.com> Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Hao A Wu <hao.a.wu@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
parent
fd8c6bed8a
commit
00acc6cbf9
@ -5,6 +5,7 @@
|
||||
# the capsule runtime services are ready.
|
||||
#
|
||||
# Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
|
||||
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
|
||||
# SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
#
|
||||
##
|
||||
@ -21,20 +22,20 @@
|
||||
#
|
||||
# The following information is for reference only and not required by the build tools.
|
||||
#
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
|
||||
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
|
||||
#
|
||||
|
||||
[Sources]
|
||||
CapsuleService.c
|
||||
CapsuleService.h
|
||||
|
||||
[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
|
||||
[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
|
||||
SaveLongModeContext.c
|
||||
|
||||
[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
|
||||
[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
|
||||
CapsuleCache.c
|
||||
|
||||
[Sources.Ia32, Sources.X64, Sources.EBC]
|
||||
[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
|
||||
CapsuleReset.c
|
||||
|
||||
[Sources.ARM, Sources.AARCH64]
|
||||
|
Loading…
x
Reference in New Issue
Block a user